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參數(shù)資料
| 型號(hào)： | MTA81010S-LPI/SO |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁數(shù)： | 58/76頁 |
| 文件大?。?/td> | 745K |
| 代理商： | MTA81010S-LPI/SO |
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1995 Microchip Technology Inc.
DS39005D-page 61
MTA81010
19.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP.
Accordingly, the following bus conditions have been
defined (Figure 19-1):
19.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
19.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START. All
commands must be preceded by a START.
19.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
19.4
Data Valid (D)
The state of the data line represents valid data when,
after a START, the data line is stable for the duration of
the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START and
terminated with a STOP. The number of the data bytes
transferred
between
the
START
and
STOP
is
determined by the master device and is theoretically
unlimited, although only the last eight will be stored
when doing a write operation. When an overwrite does
occur it will replace data in a first in first out fashion.
19.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse.
Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP.
Note:
The 24LC01B does not generate any
acknowledge
bits
if
an
internal
programming cycle is in progress.
FIGURE 19-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
AAAA
A
SCL
SDA
(A)
(B)
START
(C)
(A)
(D)
Address
or
Acknowledge
Valid
Data Allowed
to Change
STOP
Condition
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| MTA81010-LPI/P | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP28 |
| MTA81010S-RCI/SO | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28 |
| MTA81010-XTI/P | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP28 |
| MTA81010T-XT/SO | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28 |
| MTA81010S-XTI/SO | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28 |
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