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參數(shù)資料
| 型號： | MTA81010S-LPI/SO |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁數(shù)： | 60/76頁 |
| 文件大?。?/td> | 745K |
| 代理商： | MTA81010S-LPI/SO |
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1995 Microchip Technology Inc.
DS39005D-page 63
MTA81010
19.7
Byte Write
Following the start signal from the master, the device
code (4-bits), the don't care bits (3-bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte
transmitted by the master is the word address and will
be written into the address pointer of the 24LC01B.
After receiving another acknowledge signal from the
24LC01B the master device will transmit the data word
to be written into the addressed memory location. The
24LC01B
acknowledges
again
and
the
master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24LC01B will not
generate acknowledge signals (Figure 19-3).
19.8
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC01B in the same way
as in a byte write. But instead of generating a stop
condition the master transmits up to eight data bytes to
the 24LC01B which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll
over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an
internal write cycle will begin (Figure 19-4).
FIGURE 19-3: BYTE WRITE
FIGURE 19-4: PAGE WRITE
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
CONTROL
BYTE
WORD
ADDRESS
DATA
S
T
O
P
S
T
A
R
T
A
C
K
S
P
A
C
K
A
C
K
BUS
MASTER
SDA LINE
BUS
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
S
T
O
P
S
T
A
R
T
A
C
K
S
P
A
C
K
A
C
K
ACTIVITY:
A
C
K
A
C
K
DATA n+1
DATA n+7
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|---|---|
| MTA81010-LPI/P | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP28 |
| MTA81010S-RCI/SO | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28 |
| MTA81010-XTI/P | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP28 |
| MTA81010T-XT/SO | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28 |
| MTA81010S-XTI/SO | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28 |
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