參數(shù)資料
型號: MTA81010S-RCI/SO
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28
封裝: 0.300 INCH, SOIC-28
文件頁數(shù): 13/76頁
文件大小: 745K
代理商: MTA81010S-RCI/SO
MTA81010
DS39005D-page 20
1995 Microchip Technology Inc.
4.0
I/O REGISTERS (PORTS)
The I/O registers can be written and read under
program control like any other register of the register
file. However, "read" instructions (e.g., MOVF 6,W)
always read the I/O pins, regardless if a pin is defined
as "input" or "output." Upon a RESET, all I/O ports are
defined as "input" (= high impedance mode) as the I/O
control registers (TRISA, TRISB) are all set to "ones."
The
execution
of
a
"TRIS
f"
instruction
with
corresponding "zeros" in the W-register is necessary to
define any of the I/O pins as output.
4.1
f5 (Port A)
4-bit I/O register. Low order 4 bits only are used
(RA3:RA0). Bits 4-7 are unimplemented and read as
"zeros."
4.2
f6 (Port B)
8-bit I/O register.
4.3
f7
General purpose register.
4.4
I/O Interfacing
The equivalent circuit for an I/O port bit is shown in
Figure 4-1. All ports may be used for both input and
output operations. For input operations these ports are
non-latching. Any input must be present until read by
an input instruction (e.g., MOVF 6, W). The outputs are
latched and remain unchanged until the output latch is
rewritten.
To
use
a
port
pin
as
output,
the
corresponding direction control bit (in TRISA, TRISB)
must be set to zero. For use as an input, the
corresponding TRIS bit must be "one". Any I/O pin can
be programmed individually as input or output.
FIGURE 4-1:
EQUIVALENT CIRCUIT FOR A SINGLE I/0 PIN
DQ
CK
Q
VDD
VSS
P
I/O Pin
From
Data
Bus
Write
To Data Bus
From
W-Register
TRIS f
"Read"
Reset
Data
Latch
Q1
N
Q2
DQ
CK
Q
Set
I/O
Control
Latch
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