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參數(shù)資料
| 型號： | MTA85412-04I/SS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO20 |
| 封裝： | 0.209 INCH, PLASTIC, SSOP-20 |
| 文件頁數(shù)： | 8/72頁 |
| 文件大?。?/td> | 760K |
| 代理商： | MTA85412-04I/SS |
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MTA85XXX
DS40115C-page 16
1995 Microchip Technology Inc.
5.8
I/O Registers (Ports)
The I/O registers can be written and read under
program control like any other register of the register
file.
However,
"read"
instructions
(e.g.,
MOVF
PORTB,W
) always read the I/O pins, regardless if a pin
is defined as "input" or "output." Upon a RESET, all I/O
ports are defined as "input" (= hi impedance mode) as
the I/O control registers (TRISA, TRISB) are all set to
'1's.
The
execution
of
a
"TRIS
f"
instruction
with
corresponding ’0’s in the W register is necessary to
define any of the I/O pins as output.
5.8.1
PORTA f5
4-bit I/O register. Low-order 4-bits only are used (RA3:
RA0). Bits (STATUS <7:4>) are unimplemented and
read as '0's.
5.8.2
PORTB f6
8-bit I/O register. Note that RB7 is tied to SEE VDD on
MTA85XIX devices.
5.8.3
I/O INTERFACING
The equivalent circuit for an I/O port bit is shown in
Figure 5-7. All ports may be used for both input and
output operations. For input operations these ports are
non-latching. Any input must be present until read by
an input instruction (e.g., MOVF PORTB, W). The out-
puts are latched and remain unchanged until the output
latch is rewritten. To use a port pin as output, the
corresponding direction control bit (in TRISA, TRISB)
must be set to '0'. For use
as an input, the
corresponding TRIS bit must be '1'. Any I/O pin can be
programmed individually as an input or output.
FIGURE 5-7:
EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN
FIGURE 5-8:
I/O PORT READ/WRITE TIMING
DQ
CK
Q
VDD
VSS
P
I/O Pin
From
Data
Bus
Write
To Data Bus
From
W-Register
TRIS f
"Read"
Reset
Data
Latch
Q1
N
Q2
DQ
CK
Q
Set
I/O
Control
Latch
Note:
This example shows a write to PORTB
followed by a read from PORTB.
Note that:
data setup time = (0.25 TCY - TPD)
where TCY = instruction cycle.
Therefore, at higher clock frequencies,
a write followed by a read may be problematic.
TPD = propagation delay
PC
PC + 1
PC + 2
PC + 3
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2 Q3 Q4
Instruction
fetched
RB7:RB0>
MOVWF PORTB
write to
PORTB
NOP
Port pin
sampled here
NOP
MOVF PORTB,W
Instruction
executed
MOVWF PORTB
NOP
Read PORTB
TPD
Execute
MOVF PORTB,W
Execute
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