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參數(shù)資料
| 型號： | MTA85802S-10I/SS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 10 MHz, RISC MICROCONTROLLER, PDSO20 |
| 封裝： | 0.209 INCH, PLASTIC, SSOP-20 |
| 文件頁數(shù)： | 32/72頁 |
| 文件大小： | 760K |
| 代理商： | MTA85802S-10I/SS |
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MTA85XXX
DS40115C-page 38
1995 Microchip Technology Inc.
TABLE 15-6:
AC CHARACTERISTICS OF EEPROM
AC CHARACTERISTICS
Parameter
Symbol
Standard Mode VCC = 4.5-5.5V
Fast Mode
Units
Remarks
Min
Max
Min
Max
Clock frequency
FCLK
01000400
kHz
Clock high time
THIGH
4000
—
600
—
ns
Clock low time
TLOW
4700
—
1300
—
ns
SDA and SCL rise time
TR
—
1000
UF
300
ns
Note 2
SDA and SCL fall time
TF
—
300
UF
300
ns
Note 2
START condition hold time
THD:STA
4000
—
600
—
ns
After this period the first clock
pulse is generated
START condition setup time
TSU:STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
—
0
—
ns
Note 1
Data input setup time
TSU:DAT
250
—
100
—
ns
STOP condition setup time
TSU:STO
4000
—
600
—
ns
Output valid from clock
TAA
—
3500
—
900
ns
Note 1
Bus free time
TBUF
4700
—
1300
—
ns
Time the bus must be free
before a new transmission can
start
Output fall time from VIH minimum to
VIL maximum
TOF
—
250
20+0.1
CB
250
ns
Note 2, CB
≤ 100 pF
Input filter spike suppression
(SDA and SCL pins)
TSP
N/A
0
50
ns
Note 3
Write cycle time
TWR
—
10
—
10
ms
Byte or Page mode
Endurance
—
100,000
—
100,000
—
E/W
cycles
Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Note 2: Not 100% tested. CB = total capacitance of one bus line in pF.
Note 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI specification for standard operation.
15.4
Electrical Structure of Pins
FIGURE 15-1: ELECTRICAL STRUCTURE OF
I/O PINS (RA, RB)
VDD
VSS
RIN
Input
Buffer
I/O pin
P
N
VSS
FIGURE 15-2: ELECTRICAL STRUCTURE OF
MCLR AND T0CKI PINS
VSS
RIN
Schmitt Trigger
MCLR,
N
T0CKI
Input Buffer
Notes to Figure 15-1 and Figure 15-2: The diodes and the grounded gate (or output driver) NMOS device are carefully
designed to protect against ESD (Electrostatic discharge) and EOS (Electrical overstress). RIN is a small resistance to
further protect the input buffer from ESD.
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