參數(shù)資料
型號(hào)： MTA85811-04I/SS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO20
封裝： 0.209 INCH, PLASTIC, SSOP-20
文件頁(yè)數(shù)： 48/72頁(yè)
文件大小： 760K
代理商： MTA85811-04I/SS
MTA85XXX
DS40115C-page 52
1995 Microchip Technology Inc.
17.0
EEPROM BUS DESCRIPTION
The MTA85XXX supports a bidirectional two wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device (microcontroller) which
generates the
serial clock (SCL), controls the bus
access,
and
generates
the
START
and
STOP
conditions, while the EEPROM (24LC01B/02B) works
as slave. Both master and slave can operate as
transmitter
or
receiver
but
the
master
device
determines which mode is activated.
17.1
Bus Characteristics
The following bus protocol has been defined:
- Data transfer may be initiated only when the
bus is not busy.
- During data transfer, the data line must
remain stable whenever the clock line is
HIGH. Changes in the data line while the
clock line is HIGH will be interpreted as a
START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 17-1):
17.1.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
17.1.2
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
17.1.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
17.1.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
sixteen will be stored when doing a write operation.
When an overwrite does occur it will replace data in a
first in first out fashion.
17.1.5
ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
* Note: The EEPROM does not generate any
acknowledge bits if an internal pro-
gramming cycle is in progress.
FIGURE 17-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
AAAA
AA
SCL
SDA
(A)
(B)
START
(C)
(A)
(D)
Address
or
Acknowledge
Valid
Data Allowed
to Change
STOP
Condition
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