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參數(shù)資料
| 型號(hào)： | MTA85811-04I/SS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO20 |
| 封裝： | 0.209 INCH, PLASTIC, SSOP-20 |
| 文件頁數(shù)： | 56/72頁 |
| 文件大?。?/td> | 760K |
| 代理商： | MTA85811-04I/SS |
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MTA85XXX
DS40115C-page 6
1995 Microchip Technology Inc.
2.3
Data Register File
The 8-bit
data bus connects two basic functional
elements together: the Register File composed of
addressable 8-bit registers including the I/O Ports, and
an 8-bit wide Arithmetic Logic Unit. The 32 bytes of
RAM are directly addressable while a "banking"
scheme, with banks of 16 bytes each, is employed to
address larger data memories (Figure 5-1). Data can
be addressed direct, or indirect using the file select
register (f4). Immediate data addressing is supported
by special "literal" instructions which load data from
program memory into the W register.
The register file is divided into two functional groups:
operational registers and general purpose registers.
The operational registers include the Real Time Clock
Counter (T0CKI) register, the Program Counter (PC),
the Status Register, the I/O registers (PORTs), and the
File Select Register. The general purpose registers are
used for data and control information under command
of the instructions.
In addition, special purpose registers
are used to
control the I/O port configuration, and the prescaler
options.
2.4
Arithmetic/Logic Unit (ALU)
The 8-bit wide ALU contains one temporary working
register (W Register). It performs arithmetic and
Boolean functions between data held in the W Register
and any file register. It also does single operand
operations on either the W register or any file register.
2.5
Program Memory
512 or 2048 words of 12-bit wide on-chip program
memory (EPROM) can be directly addressed.
Sequencing of microinstructions is controlled via the
Program Counter (PC) which automatically increments
to
execute
in-line
programs.
Program
control
operations,
supporting
direct,
indirect,
relative
addressing modes, can be performed by Bit Test and
Skip instructions, Call instructions, Jump instructions or
by loading computed addresses into the PC.
In
addition, an on-chip two-level stack is employed to
provide easy to use subroutine nesting.
FIGURE 2-2:
CLOCKS/INSTRUCTION CYCLE
Note:
For additional details on the PIC16C5X architecture, please refer to document # DS30236.
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
(Program counter)
OSC2/CLKOUT
(RC mode)
PC
PC+1
PC+2
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
Internal
phase
clock
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