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參數(shù)資料
| 型號(hào)： | MUAA2K80-30QGI |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 395K |
| 代理商： | MUAA2K80-30QGI |
MUAA Routing CoProcessor (RCP) Family
Timing Diagrams
18
Rev. 3
TIMING DIAGRAMS
Figure 5: Sync Port Cycle
t15
t15
t5
t5
t7
t6
t11
t10
t4
t14
t3
t3
t9
t8
t13
t16
t12
t16B
t16A
t2
t1
Data
Data
Data
Data
op
op
load
load
CLK
/DINE
DIN(31:0)
OP(3:0)
DINREADY
/FF
/MF
DOUT(31:0)
/DOUTVALID
/DOUTE
/OE
read1
readn
Table 7: Sync Port Cycle
- 20
- 30
No.
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t16A
t16B
Name
tDVCH
tCHDX
tCHDRV
tCHMV
tCHQV
tCHQZ
tCHQX
tQEVCH
tCHQEX
tGHQZ
tGLQX
tDEVCH
tCHDEX
tCHFV
tCHQVV
tCHCH
tCHCL
tCLCH
Min.
5
3
Max.
Min.
7
4
Max.
Comment
DIN(31:0), OP(3:0) setup to CLK HIGH
CLK HIGH to DIN(31:0), OP(3:0) hold
CLK HIGH to DINREADY valid
CLK HIGH to /MF valid
CLK HIGH to DO valid
CLK HIGH to DO Hi-Z
CLK HIGH to DO active
/DOUTE setup to CLK HIGH
CLK HIGH to /DOUTE hold
/OE to DO Hi-Z
/OE to DO active
/DINE setup to CLK HIGH
CLK HIGH to DINE hold
CLK HIGH to /FF valid
CLK HIGH to /DOUTVALID
CLK period
CLK HIGH time
CLK LOW time
16
10
15
2.5
18
12
18
4
0.5
3
5
3
0.5
3
5
3
0.5
4
7
4
0.5
4
7
4
3
4
10
10
12
12
20
8
8
30
12
12
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