參數(shù)資料
型號： MV80C51C-12R
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44
封裝： 1.40 MM HEIGHT, QFP-44
文件頁數(shù)： 90/170頁
文件大?。?/td> 4133K
代理商： MV80C51C-12R
26
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Note:
1. This mode is available in all devices, although only ATtiny5/10 are equipped with an ADC
Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is exe-
cuted. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to
write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately
after waking up.
7.4.2
PRR – Power Reduction Register
Bits 7:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 1 – PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog com-
parator cannot use the ADC input MUX when the ADC is shut down.
The ADC is available in ATtiny5/10, only.
Bit 0 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, opera-
tion will continue like before the shutdown.
101
Reserved
110
Reserved
111
Reserved
Table 7-2.
Sleep Mode Select
SM2
SM1
SM0
Sleep Mode
Bit
7
6
5
4
3
2
1
0
–
PRADC
PRTIM0
PRR
Read/Write
R
R/W
Initial Value
0
相關PDF資料
PDF描述
MF180C51T-16D 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
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