參數(shù)資料
型號： MV80C51T-16D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
封裝： 1.40 MM HEIGHT, QFP-44
文件頁數(shù)： 153/170頁
文件大?。?/td> 4133K
代理商： MV80C51T-16D
83
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Figure 13-1. Analog to Digital Converter Block Schematic
13.4
Starting a Conversion
Make sure the ADC is powered by clearing the ADC Power Reduction bit, PRADC, in the Power Reduction Regis-
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as
long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a differ-
ent data channel is selected while a conversion is in progress, the ADC will finish the current conversion before
performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting
the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger
trigger sources. When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a con-
version is started. This provides a method of starting conversions at fixed intervals. If the trigger signal still is set
when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger
signal during conversion, the edge will be ignored. Note that an interrupt flag will be set even if the specific interrupt
is disabled. A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be
cleared in order to trigger a new conversion at the next interrupt event.
ADMUX
DECODER
8-BIT DATA BUS
MUX1
MUX0
ADCSRA
ADCL
ADPS0
ADEN
ADPS1
ADPS2
AD
A
T
E
ADIF
ADSC
TRIGGER
SELECT
VREF
ADTS2:0
ST
AR
T
PRESCALER
ADC7:0
CONVERSION LOGIC
8-BIT DAC
ADCSRB
-
+
ADC3
ADC2
ADC1
ADC0
VCC
INPUT
MUX
INTERR
UPT
FLA
GS
ADIE
ADC IRQ
SAMPLE & HOLD
COMPARATOR
CHANNEL
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