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參數(shù)資料
| 型號： | MV80C51T-16D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 130/170頁 |
| 文件大?。?/td> | 4133K |
| 代理商： | MV80C51T-16D |
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62
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
PWM). For non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared or toggle at a
compare match (“Compare Match Output Unit” on page 60)
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 69.
11.8.1
Normal Mode
The simplest mode of operation is the Normal mode (WGM03:0 = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum
16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Coun-
ter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 flag in
this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOV0 flag, the timer resolution can be increased by software. There are no
special cases to consider in the Normal mode, a new counter value can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the
external events must not exceed the resolution of the counter. If the interval between events are too long, the timer
overflow interrupt or the prescaler must be used to extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
11.8.2
Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM03:0 = 4 or 12), the OCR0A or ICR0 Register are used to manipu-
late the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches
either the OCR0A (WGM03:0 = 4) or the ICR0 (WGM03:0 = 12). The OCR0A or ICR0 define the top value for the
counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also
simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 11-8 on page 62. The counter value (TCNT0) increases
until a compare match occurs with either OCR0A or ICR0, and then counter (TCNT0) is cleared.
Figure 11-8.
CTC Mode, Timing Diagram
An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF0A or
ICF0 flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler
routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when
the counter is running with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR0A or ICR0 is lower than the current value of
TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value
(0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is
TCNTn
OCnA
(Toggle)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1
4
Period
2
3
(COMnA1:0 = 1)
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