參數(shù)資料
型號(hào): MVTX2601
廠商: Zarlink Semiconductor Inc.
英文描述: Unmanaged 24-Port 10/100 Mbps Ethernet Switch
中文描述: 非托管的24端口10/100 Mbps以太網(wǎng)交換機(jī)
文件頁數(shù): 65/91頁
文件大?。?/td> 686K
代理商: MVTX2601
MVTX2601
Data Sheet
65
Zarlink Semiconductor Inc.
12.10.5 DTST – Data read back register
CPU Address: hF04
Accessed by serial interface (RO)
This register provides various internal information as selected in DPST bit [4:0]. Refer to the PHY Control
Application Note.
When bit is 1:
Bit [0] – Flow control enable
Bit [1] – Full duplex port
Bit [2] – Fast Ethernet port
Bit [3] – Link is down
Bit [7:4] – Reserved
12.10.6 PLLCR - PLL Control Register
CPU Address: hF05
Accessed by serial interface (RW)
Bit [3]
Bit [7]
Must be '1'
Selects strap option or LCLK/OECLK registers
0 - Strap option (default)
1 - LCLK/OECLK registers
12.10.7 LCLK - LA_CLK delay from internal OE_CLK
CPU Address: hF06
Accessed by serial interface (RW)
PD[12:10] LCLK Delay
000b 80h 8 Buffers Delay
001b 40h 7 Buffers Delay
010b 20h 6 Buffers Delay
011b 10h 5 Buffers Delay (Recommend)
100b 08h 4 Buffers Delay
101b 04h 3 Buffers Delay
110b 02h 2 Buffers Delay
111b 01h 1 Buffers Delay
The LCLK delay from SCLK is the sum of the delay programmed in here and the delay in OECLK register.
7
4
3
2
1
0
Inkdn
FE
Fdpx
FcEn
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