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參數(shù)資料
| 型號(hào)： | MVTX2603 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch |
| 中文描述： | 非托管的24端口的10/100 Mb 2端口千兆以太網(wǎng)交換機(jī)1 |
| 文件頁數(shù)： | 12/109頁 |
| 文件大小： | 803K |
| 代理商： | MVTX2603 |
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MVTX2603
Data Sheet
12
Zarlink Semiconductor Inc.
2.2.1 Start Condition
Generated by the master (in our case, the MVTX2603). The bus is considered to be busy after the Start condition is
generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line.
Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High
period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I
2
C bus is
free, both lines are High.
2.2.2 Address
The first byte after the Start condition determines which slave the master will select. The slave in our case is the
EEPROM. The first seven bits of the first data byte make up the slave address.
2.2.3 Data Direction
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master
transmitter sets this bit to W; a master receiver sets this bit to R.
2.2.4 Acknowledgment
Like all clock pulses, the acknowledgment-related clock pulse is generated by the master. However, the transmitter
releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down the
SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An
acknowledgment pulse follows every byte transfer.
If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the
transfer.
If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let
the master generate the Stop condition.
2.2.5 Data
After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an
acknowledge bit. Data is transferred MSB first.
2.2.6 Stop Condition
Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop condition
occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line.
The I
2
C interface serves the function of configuring the MVTX2603 at boot time. The master is the MVTX2603 and
the slave is the EEPROM memory.
2.3 Synchronous Serial Interface
The synchronous serial interface serves the function of configuring the MVTX2603
not
at boot time but via a PC.
The PC serves as master and the MVTX2603 serves as slave. The protocol for the synchronous serial interface is
nearly identical to the I
2
C protocol. The main difference is that there is no acknowledgment bit after each byte of
data transferred.
The unmanaged MVTX2603 uses a synchronous serial interface to program the internal registers. To reduce the
number of signals required, the register address, command and data are shifted in serially through the D0 pin.
STROBE- pin is used as the shift clock. AUTOFD- pin is used as data return path.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MVTX2603AG | Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch |
| MVTX2604 | Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch |
| MVTX2604AG | Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch |
| MVTX2801 | Unmanaged 4-Port 1000 Mbps Ethernet Switch |
| MVTX2801AG | Unmanaged 4-Port 1000 Mbps Ethernet Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MVTX2603A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Unmanaged 24 port 10/100Mb + 2 port 1Gb Ethernet switch |
| MVTX2603AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch |
| MVTX2603AG2 | 制造商:Microsemi Corporation 功能描述: |
| MVTX2604 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch |
| MVTX2604A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MVTX260x Physical Port Control |
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