參數(shù)資料
型號(hào): MVTX2603
廠商: Zarlink Semiconductor Inc.
英文描述: Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch
中文描述: 非托管的24端口的10/100 Mb 2端口千兆以太網(wǎng)交換機(jī)1
文件頁(yè)數(shù): 73/109頁(yè)
文件大小: 803K
代理商: MVTX2603
MVTX2603
Data Sheet
73
Zarlink Semiconductor Inc.
Bit [5] – Signal detect (when PCS interface mode)
Bit [6] – 2 G signal detect (2 G mode only)
Bit [7] – Module detected (for hot swap purpose)
13.9.6 PLLCR - PLL Control Register
CPU Address: hF05
Accessed by serial interface (RW)
Bit [3]
Must be '1'
Bit [7]
Selects strap option or LCLK/OECLK registers
0 - Strap option (default)
1 - LCLK/OECLK registers
13.9.7 LCLK - LA_CLK delay from internal OE_CLK
CPU Address: hF06
Accessed by serial interface (RW)
PD[12:10] LCLK Delay
000b 80h 8 Buffers Delay
001b 40h 7 Buffers Delay
010b 20h 6 Buffers Delay
011b 10h 5 Buffers Delay (Recommend)
100b 08h 4 Buffers Delay
101b 04h 3 Buffers Delay
110b 02h 2 Buffers Delay
111b 01h 1 Buffers Delay
The LCLK delay from SCLK is the sum of the delay programmed in here and the delay in OECLK register.
13.9.8 OECLK - Internal OE_CLK delay from SCLK
CPU Address: hF07
Accessed by serial interface (RW)
The OE_CLK is used for generating the OE0 and OE1 signals.
PD[15:13] OECLK Delay
000b 80h 8 Buffers Delay
001b 40h 7 Buffers Delay (Recommend)
010b 20h 6 Buffers Delay
011b 10h 5 Buffers Delay
100b 08h 4 Buffers Delay
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MVTX2603A 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Unmanaged 24 port 10/100Mb + 2 port 1Gb Ethernet switch
MVTX2603AG 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch
MVTX2603AG2 制造商:Microsemi Corporation 功能描述:
MVTX2604 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch
MVTX2604A 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MVTX260x Physical Port Control