參數(shù)資料
型號: MVTX2802
廠商: Zarlink Semiconductor Inc.
英文描述: Managed 4-Port 1000 Mbps Ethernet Switch
中文描述: 管理4端口1000 Mbps以太網(wǎng)交換機
文件頁數(shù): 113/154頁
文件大?。?/td> 1936K
代理商: MVTX2802
MVTX2802
Data Sheet
113
Zarlink Semiconductor Inc.
12.2 Ball- Signal Descriptions
All pins are CMOS type; all Input pins are 5 Volt tolerance, and all Output pins are 3.3 CMOS drive.
12.2.1 Ball Signal Description in Managed Mode
Ball No(s)
Symbol
I/O
Description
CPU Bus Interface
K27, L27, K30, K29, K28,
L30, N27, L29, L28, N26,
M30, M29, M28, N30, N29,
N28
P_DATA[15:0]
I/O-TS with pull up
Processor Bus Data Bit
[15:0]
J28, J27, M26
P_A[2:0]
Input
Processor Bus Address
Bit [2:0]
J29
P_WE#
Input with weak internal
pull up
CPU Bus-Write Enable
J30
P_RD#
Input with weak internal
pull up
CPU Bus-Read Enable
L26
P_CS#
Input with weak internal
pull up
Chip Select
H28
P_INT#
Output
CPU Interrupt
Frame Buffer Interface
U1, U2, N4, U3, U4, T1, T2,
N5, T3, T4, M4, R4, R3, R2,
R1, M5, R5, L4, P3, P2, P1,
N3, L5, N2, P5, N1, K4, M3,
M2, M1, K5, L3, J5, K2, H4,
K1, J4, J3, J2, H5, J1, H3,
H2, H1, G3, G4, G5, G2, G1,
F5, F4, F3, F2, F1, D3, E1,
E2, E3, D2., E4, C3, D1, C1,
B2
LA_D[63:0]
I/O-TS with pull up
Frame Bank A– Data
Bit [63:0]
AA1, V5, AA2, AA3, Y1, V4,
Y2, Y3, U5, W1, W2, W3, T5,
V1, V2, P4, V3
LA_A[19:3]
Output
Frame Bank A –
Address Bit [19:3]
W4
LA_A[20]
Output with pull up
Frame Bank A –
Address Bit [20]
C2
LA_CLK
Output
Frame Bank A Clock
Input
K3
LA_CS0#
Output with pull up
Frame Bank A Low
Portion Chip Selection
L1
LA_CS1#
Output with pull up
Frame Bank A High
Portion Chip Selection
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