
MVTX2802
Data Sheet
19
Zarlink Semiconductor Inc.
2.5.5 Data
After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an
acknowledge bit. Data is transferred MSB-first.
2.5.6 Stop Condition
Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop
condition occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line.
The I
2
C interface serves the function of configuring the MVTX2802AG at boot time. The master is the
MVTX2802AG, and the slave is the EEPROM memory.
2.6 Synchronous Serial Interface
The synchronous serial interface serves the function of configuring the MVTX2802AG
not
at boot time but via a
PC. The PC serves as master and the MVTX2802AG serves as slave. The protocol for the synchronous serial
interface is nearly identical to the I
2
C protocol. The main difference is that there is no acknowledgment bit after
each byte of data transferred.
The unmanaged MVTX2802AG uses a synchronous serial interface to program the internal registers. To reduce
the number of signals required, the register address, command and data are shifted in serially through the
PS_DI pin. PS_STROBE- pin is used as the shift clock. PS_DO pin is used as data return path.
Each command consists of four parts.
START pulse
Register Address
Read or Write command
Data to be written or read back
Any command can be aborted in the middle by sending an ABORT pulse to the MVTX2802AG.
A START command is detected when PS_DI is sampled high at PS_STROBE - leading edge, and PS_DI is
sampled low when PS_STROBE- falls.
An ABORT command is detected when PS_DI is sampled low at PS_STROBE - leading edge, and PS_DI is
sampled high when PS_STROBE - falls.
2.6.1 Write Command
PS-STROBE-
PS_DI
A0
A2
...
A9
A10
A11
A1
W
D0
D1
D2
D3
D4
D5
D6
D7
START
ADDRESS
COMMAND
DATA
2 Extra clocks after last
transfer