參數(shù)資料
型號： MX25L1605DMI-12G
廠商： MACRONIX INTERNATIONAL CO LTD
元件分類： PROM
英文描述： 8M X 2 FLASH 2.7V PROM, PDSO16
封裝： 0.300 INCH, ROHS COMPLIANT, MS-013, SOP-16
文件頁數(shù)： 56/56頁
文件大?。?/td> 3202K
代理商： MX25L1605DMI-12G
9
MX25L1605D
MX25L3205D
MX25L6405D
P/N: PM1290
REV. 1.5, APR. 29, 2009
Table 4. COMMAND DEFINITION
Command
(byte)
WREN (write
enable)
WRDI (write
disable)
RDID
(read
identific-
ation)
RDSR
(read status
register)
WRSR
(write status
register)
READ (read
data)
FAST READ
(fast read
data)
2READ (2
x I/O read
command)
Note1
1st byte
06 (hex)
04 (hex)
9F (hex)
05 (hex)
01 (hex)
03 (hex)
0B (hex)
BB (hex)
2nd byte
AD1
ADD(2)
3rd byte
AD2
ADD(2) &
Dummy(2)
4th byte
AD3
5th byte
Dummy
Action
sets the
(WEL) write
enable latch
bit
resets the
(WEL) write
enable latch
bit
outputs
JEDEC
ID: 1-byte
Manufact-
urer ID &
2-byte Device
ID
to read out
the values
of the status
register
to write new
values to
the status
register
n bytes read
out until CS#
goes high
n bytes read
out until CS#
goes high
n bytes read
out by 2 x I/
O until CS#
goes high
Command
(byte)
SE (sector
erase)
BE (block
erase)
CE (chip
erase)
PP (page
program)
CP
(continuously
program
mode)
DP (Deep
power down)
RDP
(Release
from deep
power down)
RES (read
electronic ID)
1st byte
20 (hex)
D8 (hex)
60 or C7 (hex)
02 (hex)
AD (hex)
B9 (hex)
AB (hex)
2nd byte
AD1
x
3rd byte
AD2
x
4th byte
AD3
x
5th byte
Action
to erase the
selected
sector
to erase the
selected
block
to erase
whole chip
to program
the selected
page
continously
program
whole chip,
the address
automatically
increases
enters deep
power down
mode
release from
deep power
down mode
to read out
1-byte Device
ID
Command
(byte)
REMS (read
electronic
manufacturer
& device ID)
REMS2 (read
ID for 2x I/O
mode)
ENSO (enter
secured
OTP)
EXSO (exit
secured
OTP)
RDSCUR
(read security
register)
WRSCUR
(write security
register)
ESRY
(enable SO
to output RY/
BY#)
DSRY
(disable SO
to output RY/
BY#)
1st byte
90 (hex)
EF (hex)
B1 (hex)
C1 (hex)
2B (hex)
2F (hex)
70 (hex)
80 (hex)
2nd byte
x
3rd byte
x
4th byte
ADD (Note 2) ADD (Note 2)
5th byte
Action
output the
Manufacturer
ID & Device
ID
output the
Manufacturer
ID & Device
ID
to enter
the 512-bit
secured OTP
mode
to exit the
512-bit
secured OTP
mode
to read value
of security
register
to set the
lock-down bit
as "1" (once
lock-down,
cannot be
updated)
to enable SO
to output RY/
BY# during
CP mode
to disable SO
to output RY/
BY# during
CP mode
Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SI/SIO0 which is different from
1 x I/O condition.
Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hid-
den mode.
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