參數(shù)資料
型號(hào): MX7705
廠商: Maxim Integrated Products, Inc.
英文描述: 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC
中文描述: 16位、低功耗、2通道、Σ-Δ ADC
文件頁(yè)數(shù): 26/34頁(yè)
文件大?。?/td> 664K
代理商: MX7705
M
Reset
Drive
RESET
low to reset the MX7705 to power-on reset
status.
DRDY
goes high and all communication to the
MX7705 is ignored while
RESET
is low. Upon releasing
RESET
, the device must be reconfigured to begin a con-
version. The device returns to waiting for a write to the
communication register after a reset has been performed.
Perform a calibration sequence following a reset for
accurate conversions.
The MX7705 clock generator continues to run when
RESET
is pulled low. This allows any device running from
CLKOUT to be uninterrupted when the device is in reset.
Selecting Custom Output Data Rates and
First-Notch Frequency
The recommended frequency range of the external clock
is 400kHz to 5MHz. The output data rate and first notch
frequency are dependent on the decimation rate of the
digital filter. Table 14 shows the available decimation
rates of the digital filter. The output data rate and filter first
notch is calculated using the following formula:
(if CLKDIV = 1)
(if CLKDIV = 0)
Note:
First-notch filter frequency = output data rate.
Performing a Conversion
At power-on reset, the MX7705 expects a write to the
communications register. Writing to the communica-
tions register selects the acquisition channel, read/write
operation for the next register, power-down/normal
mode, and address of the following register to be
accessed. The MX7705 has six user-accessible regis-
ters, which control the function of the device and allow
the result to be read. Write to the communications reg-
ister before accessing any other registers.
Writing to the clock and setup registers after configuring
and initializing the host processor serial port sets up the
MX7705. Use self- or system calibrations to minimize off-
set and gain errors (see the
Calibration
section for more
details). Set FSYNC = 0 to begin calibration or conver-
sion. The MX7705 performs free-running acquisitions
when FSYNC is low (see the
Using FSYNC
section). The
μC can poll the
DRDY
bit of the communications register
and read the data register when the
DRDY
bit returns a
0. For hardware polling, the
DRDY
output goes low when
the new data is valid in the data register.
The data register can be read multiple times while the
next conversion takes place.
The flow diagram in Figure 11 shows an example
sequence required to perform a conversion on channel
1 (AIN1+ / AIN1-) after a power-on reset.
output data rate
f
Decimation Rate
CLKIN
×
=
128
output data rate
f
Decimation Rate
CLKIN
×
0 5
=
128
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
26
______________________________________________________________________________________
Table 14. Filter Select and Decimation Rate
CLK
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
DECIMATION RATE
391
313
78
39
384
320
77
38
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MX7705_09 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC
MX7705_10 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC
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MX7705EPE+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 2Ch Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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