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參數(shù)資料
| 型號： | MX7705EWE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC |
| 中文描述： | 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | SOP-16 |
| 文件頁數(shù)： | 20/34頁 |
| 文件大?。?/td> | 664K |
| 代理商： | MX7705EWE |
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M
Modulator
The MX7705 performs analog-to-digital conversions
using a single-bit, 2nd-order, switched-capacitor,
sigma-delta modulator. The sigma-delta modulation
converts the input signal into a digital pulse train whose
average duty cycle represents the digitized signal infor-
mation. A single comparator within the modulator quan-
tizes the input signal at a much higher sample rate than
the bandwidth of the input.
The MX7705 modulator provides 2nd-order frequency
shaping of the quantization noise resulting from the sin-
gle-bit quantizer. The modulator is fully differential for
maximum signal-to-noise ratio and minimum suscepti-
bility to power-supply and common-mode noise. A sin-
gle-bit data stream is then presented to the digital filter
for processing to remove the frequency-shaped quanti-
zation noise.
The modulator sampling frequency is f
CLKIN
/ 128,
regardless of gain, where f
CLKIN
(CLKDIV = 0) is the
frequency of the signal at CLKIN.
Digital Filtering
The MX7705 contains an on-chip, digital lowpass filter
that processes the 1-bit data stream from the modulator
using a SINC
3
(sinx/x)
3
response. The SINC
3
filter has a
settling time of three output data periods.
Filter Characteristics
Figure 6 shows the filter frequency response. The
SINC
3
characteristic -3dB cutoff frequency is 0.262
times the first-notch frequency. This results in a cutoff
frequency of 15.72Hz for a first filter-notch frequency of
60Hz (output data rate of 60Hz). The response shown
in Figure 5 is repeated at either side of the digital filter
’
s
sample frequency, f
M
(f
M
= 19.2kHz for 60Hz output
data rate), and at either side of the related harmonics
(2f
M
, 3f
M
, etc.).
The output data rate for the digital filter corresponds with
the positioning of the first notch of the filter
’
s frequency
response. Therefore, for the plot in Figure 6, where the first
notch of the filter is 60Hz, the output data rate is 60Hz. The
notches of the SINC
3
filter are repeated at multiples of the
first notch frequency. The SINC
3
filter provides an attenua-
tion of better than 100dB at these notches.
Determine the cutoff frequency of the digital filter by load-
ing the appropriate values into the CLK, FS0, and FS1
bits in the clock register (Table 13). Programming a differ-
ent cutoff frequency with FS0 and FS1 changes the fre-
quency of the notches, but it does not alter the profile of
the frequency response.
For step changes at the input, allow a settling time
before valid data is read. The settling time depends on
the output data rate chosen for the filter. The worst-
case settling time of a SINC
3
filter for a full-scale step
input is four times the output data period. By synchro-
nizing the step input using FSYNC, the settling time
reduces to three times the output data period. If FSYNC
is high during the step input, the filter settles in three
times the output data period after FSYNC falls low.
Analog Filtering
The digital filter does not provide any rejection close to
the harmonics of the modulator sample frequency. Due
to the high oversampling ratio of the MX7705, these
bands occupy only a small fraction of the spectrum and
most broadband noise is filtered. The analog filtering
requirements in front of the MX7705 are reduced com-
pared to a conventional converter with no on-chip filtering.
In addition, the devices provide excellent common-mode
rejection of 90db to reduce the common-mode noise sus-
ceptibility.
Additional filtering prior to the MX7705 eliminates
unwanted frequencies the digital filter does not reject.
Use additional filtering to ensure that differential noise
signals outside the frequency band of interest do not
saturate the analog modulator.
If passive components are in the path of the analog
inputs when the device is in unbuffered mode, ensure
the source impedance is low enough (Figure 2) not to
introduce gain errors in the system. This significantly
limits the amount of passive anti-aliasing filtering that
can be applied in front of the MX7705 in unbuffered
mode. In buffered mode, large source impedance
causes a small DC-offset error, which can be removed
by calibration.
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
20
______________________________________________________________________________________
-160
-120
-140
-100
-80
-60
-20
-40
0
0
40
60
80
20
100 120 140 160 180 200
FREQUENCY (Hz)
G
f
= 2.4576MHz
CLK = 1
FS1 = 0
FS0 = 1
f
N
= 60Hz
Figure 6. Frequency Response of the SINC
3
Filter (Notch at 60Hz)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MX7705EWE+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 2Ch Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MX7705EWE+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 2Ch Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MX7705EWE-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MX7820 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS.1.3µ.s.8-Bit ADC with Voltage Reference and Track/Hold |
| MX7820BQ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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