參數(shù)資料
型號: MX98742
英文描述: FEBC 100 Base Fast Ethernet Bridge Controller
中文描述: FEBC 100基地快速以太網(wǎng)橋控制器
文件頁數(shù): 29/36頁
文件大小: 166K
代理商: MX98742
29
MX98745
P/N:PM0427
REV. 1.4, JUL. 8, 1998
T25
TXCLK
T22
TXD[3:0]
TXEN
TXER
T24
Figure 9-3 Trannsmit Signal Timing Relationships at the MII
T21
T23
Symbol
T21
T22
23
T24
T25
Description
TXCLK Period (Note 1)
TXCLK High Time
TXCLK Low Time
TXD[3:0]/TXEN/TXER Setup Time to TXCLK rising edge (Note 2)
TXD[3:0]/TXEN/TXER Hold Time to TXCLK rising edge (Note 2)
MIN.
40
20
18
20
15
MAX.
40
-
-
-
-
UNIT
ns
ns
ns
ns
ns
Note 1 : The accurate TXCLK frequency shall be 25 MHz
+/- 50 ppm. In PCS type MII, this signal is
outputed by MX9745. In MAC type MII, this sig-
nal is input to MX98745.
Note 2 : The setup time of an MII signal relative to an MII
clock edge is defined as the length of time be-
tween when the signal exits and remains out of
the switching region and when the clock enters
the switching region. The hold time of an MII
signal relative to an MII clock edge is defined as
the length of time between when the clock exits
the switching region and when the signal enters
the switching region. (see section 22.3 in [1])
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