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| 型號： | MX98905B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
| 中文描述： | 該MX98905是專為易于實現(xiàn)的多址/光盤局域網(wǎng)， |
| 文件頁數(shù)： | 25/86頁 |
| 文件大?。?/td> | 352K |
| 代理商： | MX98905B |
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25
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
The internal state machine will be reset after
EEPROM_STORE is finished.
This algorithm is preliminary. For actual implementa-
tion, user can contact with our FAE by calling 886-02-
7191977 for details.
10. TWISTED-PAIR INTERFACE (TPI) MODULE
The TPI has five main logical functions:
1. The Smart Squelch is responsible for determining
when valid data is present on the differential re-
ceive inputs RXIP and RXIM
2. The Collision function checks for simultaneous
transmission and reception of data on the TXOP,
TXOM, RXIP and RXIM.
3. The Link Detector/Generator checks the integrity
of the cable connecting the two twisted-pair
MAUs.
4. The Jabber disables the transmitter if it attempts
to transmit a longer-than-legal packet.
5. The TX Driver & Pre-emphasis transmit Man-
chester-encoded data to the twisted-pair network
via the summing resistors and transformer/filter.
11. SMART SQUELCH
To make sure that impulse noise on the receive
inputs will not be mistaken for a valid signal, the
ENC carries out an intelligent receive squelch on the
RX± differential inputs. The squelch circuitry uses
a mix of amplitude and timing measurements.
Smart squelch checks the signal at the start of
packet and any pulses that do not exceed the
squelch level, either positive or negative, depending
on polarity, is rejected. After this first squelch level
is overcome the opposite squelch level must be
exceeded within 150 ns. Finally, the signal goes
beyond the original squelch level within a further
150 ns in order for the input waveform not to be
rejected. The procedure entails the loss of at least
three bits at the start of each packet.
When these conditions are satisfied a control signal
will be generated to show the remainder of the cir-
cuitry that valid data is present. Then the smart
squelch circuitry is reset.
Valid data is deemed present until either squelch
level has not been generated for a time longer than
150 ns, which shows End of Packet. If good data is
detected, the squelch levels are reduced to contain
the noise effect which may lead to premature End-
of-Packet detection.
12. COLLISION
A collision is detected by the TPI module when the
receive and transmit channels are active simultane-
ously. If the TPI is receiving when a collision is
detected it is reported to the controller immediately.
If, however, the TPI is transmitting when a collision
is detected the collision is not reported until seven
bits have been received while in the collision state.
This prevents a collision from being reported
incorrectly due to noise on the network. The signal
to the controller remains for the duration of the
collision.
Approximately 1
m
s after the transmission of each
packet a signal called the Signal Quality Error (SQE)
consisting of typically 10 cycles of 10 MHz is gener-
ated. This 10 MHz signal, also called the Heartbeat,
ensures the continued functioning of the collision cir-
cuitry.
13. LINK DETECTOR/GENERATOR
This is a timer circuit that generates a link pulse as
shown in the 10BASE-T specification. With a width
of 100 ns, the pulse is transmitted every 16 ms on
the TXO+ output in the absence of transmit data.
The pulse checks the integrity of the connection to
the remote MAU, and the link detection circuit
checks for valid pulses from the remote MAU. The
link detector will disable the transmit, receive, and
collision detection functions if valid link pulses are
not received.
To determine that a good twisted-pair link exists,
the GDLNK output directly drives an LED; the LED
will be on during normal conditions.
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| MX98905B | IEEE 802.3, 10BASE5, 10BASE2 Controller and Integrated Bus Interface(IEEE 802.3, 10BASE5, 10BASE2控制器和集成總線接口) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MX98905BFC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
| MX98L715BEC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:3.3V SINGLE CHIP FAST ETHERNET NIC CONTROLLER |
| MX-9C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MX |
| MX-9G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MX |
| MX9G100B | 制造商:Panasonic Industrial Company 功能描述:90x90 gearhead for 40W motor,100:1 |
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