- 您現(xiàn)在的位置：買賣IC網 > PDF目錄376214 > MX98905B (Electronic Theatre Controls, Inc.) The MX98905 is designed for easy implementation of CSMA/CD local area networks, PDF資料下載
參數(shù)資料
| 型號： | MX98905B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
| 中文描述： | 該MX98905是專為易于實現(xiàn)的多址/光盤局域網， |
| 文件頁數(shù)： | 38/86頁 |
| 文件大?。?/td> | 352K |
| 代理商： | MX98905B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁
38
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
These four bits (IOBEN, PAGE, NEWCF and LOCKE)
can be loaded/stored from/to EEPROM.
RESV4..1 --- Reserved bits for future use.
Note:
Don't write this register through Base+09H/
Base+19H except it is confirmed that I/O Base does
not conflict with other Add_on card.
SYMBOL
BIT
DESCRIPTION
IOBEN
D0
I/O BASE ENABLE.
Power-on low
0 :
1 :
7 I/O base (compatible with DP83905)
15 I/O bases
PAGE
D1
PAGE SELECT FOR I/O BASE.
Power-on low
only valid when IOBEN and HCFRE of HCMR is high
0 :
1 :
I/O base address are the same as IOAD2..0 of Configuration A
I/O base address are redefined (see I/O Base support for more detail). This bit
will be updated automatically according to the sequence of AUTO configuration
when IOBEN is set.
NEWCF
D2
NEW CONFIGURATION LOADED TO CA, CB AND CC AFTER EESTORE IS
EXECUTED.
Power-on low
0 :
New configuration will not be loaded to CA, CB and CC after EESTORE
algorithm is executed. Compatible with DP83905.
New Configuration will be loaded to CA, CB and CC after EESTORE algorithm
is completed. Enhanced feature.
1 :
LOCKE
D3
LOCK ENABLE.
I/O base will not be changed when AUTO of HCMR is written into.
Power-on low.
0 :
1 :
Enable internal LOCK bit. Write 1 to AUTO will change I/O base
Enable internal LOCK bit. Write 1 to AUTO will not change I/O base. When this
bit is set, AUTO of HCMR has no effect. User CANNOT read the value of
Signature Register. After I/O base is determined (see Multi_lan card conflict
free for more detail), this bit should be programmed through base+09H for I/O
map or Base+19H for shared memory map.
2.2 HIDDEN CONFIGURATION REGISTER (R/W) (HCFR)(Continued)
相關PDF資料 |
PDF描述 |
|---|---|
| MX98905B | IEEE 802.3, 10BASE5, 10BASE2 Controller and Integrated Bus Interface(IEEE 802.3, 10BASE5, 10BASE2控制器和集成總線接口) |
| MX98905BFC | The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
| MXA2312A | Low Cost, +2,-2 g Dual Axis Accelerometer with Analog Outputs |
| MXA2500K | Ultra Low Cost, 【1.0 g Dual Axis Accelerometer with Absolute Outputs |
| MXA2500KV | Ultra Low Cost, 【1.0 g Dual Axis Accelerometer with Absolute Outputs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MX98905BFC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
| MX98L715BEC | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:3.3V SINGLE CHIP FAST ETHERNET NIC CONTROLLER |
| MX-9C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MX |
| MX-9G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MX |
| MX9G100B | 制造商:Panasonic Industrial Company 功能描述:90x90 gearhead for 40W motor,100:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復。