NB3N3020
http://onsemi.com
6
Table 6. AC CHARACTERISTICS (VDD = 3.3 V ±10%, GND = 0 V, TA = 40°C to +85°C) (Note 5) Symbol
Characteristic
Min
Typ
Max
Unit
fCLKIN
Crystal Input Frequency
5.0
27
MHz
fCLKIN
Clock Input Frequency
2.0
210
MHz
fCLKOUT
Output Clock Frequency
210
MHz
FNOISE
PhaseNoise Performance (fCLKout = 125 MHz, 25 MHz input)
@ 100 Hz offset from carrier
95
dBc/Hz
@ 1 kHz offset from carrier
107
dBc/Hz
@ 10 kHz offset from carrier
112
dBc/Hz
@ 100 kHz offset from carrier
117
dBc/Hz
@ 1 MHz offset from carrier
117
dBc/Hz
@ 10 MHz offset from carrier
134
dBc/Hz
Tjitter pp
CycletoCycle Jitter peak to peak (Note
6)fCLKout = 100 MHz and 125 MHz, 25 MHz input
20
36
ps
Tjitter rms
CycletoCycle Jitter rms (Note
7)fCLKout = 100 Mhz and 125 MHz, 25 MHz input
5.0
9.0
ps
Tjitter pp
Period Jitter peak to peak (Note
7)fCLKout = 100 MHz and 125 MHz, 25 MHz input
15
20
ps
Tjitter rms
Period Jitter rms (Note
7)fCLKout = 100 MHz and 125 MHz, 25 MHz input
3.0
5.0
ps
Start up time from power up
10
ms
OE
Output Enable/Disable Time
10
us
PLL settling time
3
ms
tDUTY_CYCLE
Output Clock Duty Cycle (Measured at cross point for LV PECL clock
output and VDD/2 for LVCMOS/ LVTTL clock output)
45
50
55
%
tR
Output Rise Time (Note
5) (Measured from 20% to 80%. Figure
2) LV
PECL Output
340
700
ps
tF
Output Fall Time (Note
5) (Measured from 20% to 80%. Figure
2) LV
PECL Output
340
700
ps
tR
Output Rise Time (Measured from 0.8 to 2 V, no load) LVCMOS/ LV TTL
Output
1500
ps
tF
Output Fall Time (Measured from 2.0 V to 0.8 V, no load) LVCMOS/ LV
TTL Output
1500
ps
tR/ tF
Input Rise time/ Fall time for LV CMOS/ LV TTL clock input [X1/CLK]
0
1500
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
5. Measurement taken with outputs terminated with 50 W to VDD 2 V. See Figure 2. 6. Sampled with 1000 cycles
7. Sampled with 10000 cycles