參數(shù)資料
型號: NB7L86MMNG
廠商: ON Semiconductor
文件頁數(shù): 1/12頁
文件大?。?/td> 0K
描述: IC GATE MULTI FUNCT DIFF 16-QFN
標(biāo)準(zhǔn)包裝: 123
邏輯類型: 可配置多功能
電路數(shù): 2
輸入數(shù): 2
施密特觸發(fā)器輸入:
輸出類型: 差分
電源電壓: 2.4 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN(3x3)
包裝: 管件
其它名稱: NB7L86MMNG-ND
NB7L86MMNGOS
Semiconductor Components Industries, LLC, 2012
March, 2012 Rev. 7
1
Publication Order Number:
NB7L86M/D
NB7L86M
2.5V/3.3V 12 Gb/s Differential
Clock/Data SmartGate with
CML Output and Internal
Termination
The NB7L86M is a multifunction differential Logic Gate, which
can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1
MUX. This device is part of the GigaComm family of high
performance Silicon Germanium products. The NB7L86M is an
ultralow jitter multilogic gate with a maximum data rate of 12 Gb/s
and input clock frequency of 8 GHz suitable for Data Communication
Systems, Telecom Systems, Fiber Channel, and GigE applications.
Differential inputs incorporate internal 50
W termination resistors
and accept LVNECL (Negative ECL), LVPECL (Positive ECL),
LVCMOS, LVTTL, CML, or LVDS. The differential 16 mA CML
output provides matching internal 50
W termination, and 400 mV
output swing when externally terminated 50
W to VCC.
The device is housed in a low profile 3x3 mm 16pin QFN package.
Application notes, models, and support documentation are available
on www.onsemi.com.
Features
Maximum Input Clock Frequency up to 8 GHz
Maximum Input Data Rate up to 12 Gb/s Typical
< 0.5 ps of RMS Clock Jitter
< 10 ps of Data Dependent Jitter
30 ps Typical Rise and Fall Times
90 ps Typical Propagation Delay
2 ps Typical Within Device Skew
Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
CML Output Level (400 mV PeaktoPeak Output) Differential Output
50 W Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP
and SG Devices
These are PbFree Devices
Figure 1. Simplified Logic Diagram
D0
Q
SEL
VTD0
Q
SEL
VTD0
50 W
D0
D1
VTD1
50 W
D1
50 W
VTSEL
http://onsemi.com
QFN16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
*For additional marking information, refer to
Application Note AND8002/D.
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
16
NB7L
86M
ALYWG
G
1
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
1
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