參數(shù)資料
型號(hào): NB7VQ14MMNTXG
廠商: ON Semiconductor
文件頁(yè)數(shù): 1/10頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK BUFFER MUX 1:4 16-QFN
標(biāo)準(zhǔn)包裝: 3,000
系列: GigaComm™
類(lèi)型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: CML
頻率 - 最大: 8.5GHz
電源電壓: 1.71 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 16-QFN(3x3)
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2010
December, 2010 Rev. 0
1
Publication Order Number:
NB7VQ14M/D
NB7VQ14M
1.8V/2.5V/3.3V 8GHz /
14Gbps Differential 1:4
Clock / Data CML Fanout
Buffer w/ Selectable Input
Equalizer
MultiLevel Inputs w/ Internal Termination
Description
The NB7VQ14M is a high performance differential 1:4 CML fanout
buffer with a selectable Equalizer receiver. When placed in series with
a Clock /Data path operating up to 8 GHz or 14 Gb/s, respectively, the
NB7VQ14M inputs will compensate the degraded signal transmitted
across a FR4 PCB backplane or cable interconnect and output four
identical CML copies of the input signal with a 1.8 V, 2.5 V or 3.3 V
power supply. Therefore, the serial data rate is increased by reducing
InterSymbol Interference (ISI) caused by losses in copper
interconnect or long cables. The EQualizer ENable pin (EQEN)
allows the IN/IN inputs to either flow through or bypass the Equalizer
section. Control of the Equalizer function is realized by setting EQEN;
When EQEN is set Low, the IN/IN inputs bypass the Equalizer. When
EQEN is set High, the IN/IN inputs flow through the Equalizer. The
default state at startup is LOW. As such, NB7VQ14M is ideal for
SONET, GigE, Fiber Channel, Backplane and other Clock/Data
distribution applications.
The differential inputs incorporate internal 50
W termination
resistors that are accessed through the VT pin. This feature allows the
NB7VQ14M to accept various logic level standards, such as LVPECL,
CML or LVDS. The 1:4 fanout design was optimized for low output
skew applications.
The NB7VQ14M is a member of the GigaComm
family of high
performance clock products.
Features
Input Data Rate > 14 Gb/s, Typical
Input Clock Frequency > 8 GHz, Typical
165 ps Typical Propagation Delay
30 ps Typical Rise and Fall Times
< 15 ps Maximum Output Skew
< 0.8 ps Maximum RMS Clock Jitter
< 10 ps pp of Data Dependent Jitter
Differential CML Outputs, 400 mV PeaktoPeak, Typical
Selectable Input Equalization
Operating Range: VCC = 1.71 V to 3.6 V with GND = 0 V
Internal Input Termination Resistors, 50 W
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
QFN16
MN SUFFIX
CASE 485G
16
NB7V
Q14M
ALYWG
G
1
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
1
EQ
SIMPLIFIED BLOCK DIAGRAM
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