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參數(shù)資料
| 型號： | NBC12429 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 3.3V/5V Programmable PLL Synthesized Clock Generator(3.3V/5V可編程PLL合成時(shí)鐘發(fā)生器) |
| 中文描述： | 3.3V/5V的可編程鎖相環(huán)路合成時(shí)鐘發(fā)生器（3.3V/5V的可編程PLL頻率合成時(shí)鐘發(fā)生器） |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 351K |
| 代理商： | NBC12429 |
NBC12429, NBC12429A
http://onsemi.com
11
Most of the signals available on the TEST output pin are
usefulonlyforperformanceverificationofthedeviceitself.
However, the PLL bypass mode may be of interest at the
board levelforfunctionaldebug.When T[2:0]issetto 110,
the device is placed in PLL bypass mode. In this mode the
S_CLOCK input is fed directly into the M and N dividers.
The N divider drives the F
OUT
differential pair and the M
counter drives the TEST output pin. In this mode the
S_CLOCK input could be used for low speed board level
functional test or debug. Bypassing the PLL and driving
F
OUT
directly gives the user more control on the test clocks
sent through the clock tree. Figure 7 shows the functional
setup of the PLL bypass mode. Because the S_CLOCK is a
CMOS level the input frequency is limited to 250 MHz or
less. This means the fastest the F
OUT
pin can be toggled via
the S_CLOCK is 250 MHz as the minimum divide ratio of
the N counter is 1. Note that the M counter output on the
TESToutputwillnotbea50%dutycycleduetothewaythe
divider is implemented.
T2
T1
T0
TEST
(Pin 20)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SHIFT REGISTER OUT
HIGH
F
REF
M COUNTER OUT
F
OUT
LOW
PLL BYPASS
F
OUT
÷
4
Figure 5. Parallel Interface Timing Diagram
M[8:0]
N[1:0]
P_LOAD
VALID
t
h
t
s
M, N to P_LOAD
Figure 6. Serial Interface Timing Diagram
S_CLOCK
S_DATA
S_LOAD
Last
Bit
C1
C2
t
h
C3
S_DATA to S_CLOCK
C4
C5
C6
C7
C8
C9
C10
C11
C12
T2
T1
T0
N1
N0
M6
M5
M4
M3
M2
M1
M0
First
Bit
t
s
t
s
t
h
S_CLOCK to S_LOAD
C13
C14
M7
M8
Figure 7. Serial Test Clock Block Diagram
FDIV4
MCNT
LOW
FOUT
MCNT
FREF
HIGH
TEST
MUX
7
0
TEST
FOUT
(VIA ENABLE GATE)
N
÷
(1, 2, 4, 8)
0
1
PLL 12429
LATCH
Reset
PLOAD
M COUNTER
SLOAD
T0
T1
T2
VCO_CLK
SHIFT
REG
14--BIT
DECODE
SDATA
SCLOCK
MCNT
FREF
SEL_CLK
T2=T1=1, T0=0: Test Mode
SCLOCK is selected, MCNT is on TEST output, SCLOCK
÷
N is on FOUT pin.
PLOAD acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NBC12429A | 3.3V/5V Programmable PLL Synthesized Clock Generator(3.3V/5V可編程PLL合成時(shí)鐘發(fā)生器) |
| NBC12430 | 3.3V/5V Programmable PLL Synthesized Clock Generator(3.3V/5V可編程PLL合成時(shí)鐘發(fā)生器) |
| NBC12430A | 3.3V/5V Programmable PLL Synthesized Clock Generator(3.3V/5V可編程PLL合成時(shí)鐘發(fā)生器) |
| NBC12439A | 3.3V/5V Programmable PLL Synthesized Clock Generator(3.3V/5V可編程PLL合成時(shí)鐘發(fā)生器) |
| NBC12439 | 3.3V/5V Programmable PLL Synthesized Clock Generator(3.3V/5V可編程PLL合成時(shí)鐘發(fā)生器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NBC12429/D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3 V/5 V Programmable PLL Synthesized Clock Generator (25 to 400 MHz) |
| NBC12429_07 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V/5V Programmable PLL Synthesized Clock Generator |
| NBC12429A | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V/5V Programmable PLL Synthesized Clock Generator |
| NBC12429AFA | 功能描述:鎖相環(huán) - PLL 3.3V/5V Programmable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| NBC12429AFAG | 功能描述:鎖相環(huán) - PLL 3.3V/5V Programmable PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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