參數(shù)資料
型號: NCN6000DTBR2
廠商: ON Semiconductor
文件頁數(shù): 7/36頁
文件大?。?/td> 0K
描述: IC INTERFACE SMART CARD 20TSSOP
產(chǎn)品變化通告: Product Obsolescence 01/Jul/2009
標(biāo)準(zhǔn)包裝: 1
應(yīng)用: ATM 終端,氣泵,ISM
接口: 微控制器
電源電壓: 2.7 V ~ 6 V
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 標(biāo)準(zhǔn)包裝
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 1131 (CN2011-ZH PDF)
其它名稱: NCN6000DTBR2OSDKR
NCN6000
http://onsemi.com
15
Basic Operating Modes Flow Chart
The NCN6000 brings all the functions necessary to handle
data communication between a host computer and the smart
card. The builtin Chip Select pin provides a simple way to
share the same MPU bus with several card interface. On top
of that, the logic control are derived from specific pins,
avoiding the risk of mixing up the operation when the
interface is controlled by a low end microcontroller.
During the transaction operation, the external MPU takes
care of whatever is necessary to he data on the single
bidirectional I/O line. Leaving aside the DCDC control and
associated failures, the NCN6000 does not take any further
responsibility in the data transaction.
When the chip operates in the programming mode, the
NCN6000 provide a flexible access to set up the CRD_VCC
voltage, the CRD_CLK and the CRD_DET smart card
signals.
The external microcontroller takes care of the smart card
transaction and shall handle the interface accordingly.
Figure 7. Operating Modes Flow Chart
RESET
Vbat = OK
STAND BY MODE
SELECT OPERATING MODE
PROGRAMMING
MODE
SET NCN6000
PARAMETERS
ACTIVE MODE
SEND ATR SEQUENCE
TRANSACTION MODE
END MODE
POWER DOWN SEQUENCE
IDLE MODE
FINISH
PWR_ON = H
CS = H
PGM = H
PGM = L
CS = L
PGM = H
CS = L
LATCH NCN6000
PARAMETERS
PGM = H
CS = H
Standby Mode
The Standby Mode allows the NCN6000 to detect a card
insertion, keeping the power consumption at a minimum.
The power supply CRD_VCC is not applied to the card, until
the external controllers set PWR_ON = H with CS = L.
Standby Mode
Logic Conditions:
Card Output:
CS
= H
PWR_ON = H
A0
= Z
A1
= Z
PGM
= Z
I/O
= Z
RESET
= Z
CRD_VCC = 0 V
CRD_CLK = L
CRD_RST = L
CRD_IO
= L
When a card is inserted, the internal logic filters the signal
present pin 11, then asserts the INT pin to Low if the pulse
applied to CRD_DET is longer than 150
ms. The external
MPU shall run whatever is necessary to handle the card.
The INT is cleared (return to High) when a positive going
transition is asserted to either the CS or to the PWR_ON
signal logically combined with Chip Select = Low.
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