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參數(shù)資料
| 型號： | NCP1927DR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 531K |
| 描述： | IC CTLR PFC/FLYBACK 16-SOIC |
| 標準包裝： | 2,500 |
| 系列： | * |
NCP1927
http://onsemi.com
10
DETAILED OPERATING DESCRIPTION
INTRODUCTION
The NCP1927 is a combination power factor correction
(PFC) and flyback controller optimized for use in Flat Panel
TVs. This device includes all the features needed to
implement a highly efficient and compact power supply. It
integrates a critical conduction mode (CrM) PFC controller
and a fixedfrequency current mode flyback controller with
proper sequencing for simplified system design.
This device includes frequency jittering, a shutdown
input, an inverter enable output, a go to standby input, and
a dedicated pin for under/overvoltage protection.
SUPPLY SEQUENCING
The flyback controller of the NCP1927 is enabled once
V
CC
reaches V
CC(on)
, provided it is not in thermal shutdown
and has not been latched off or shutdown. Once the flyback
controller is enabled, a softstart timer is activated, and it
begins switching. The softstart timer provides a ramp
signal that increases over t
SSTART
(typically 4.0 ms). This
ensures that the peak current gradually increases to
minimize power component stress and limit output voltage
overshoot. Frequency jittering is disabled while the
softstart timer is running.
Once the flyback controller detects regulation on the
output (it is no longer in overload), the PFC controller can
be enabled. As soon as the PFC controller is enabled, the
error amplifier begins to source its maximum output current,
I
EA(MAX)
, (typically 20 mA) to linearly charge the PControl
pin capacitor (C
PControl
). Softstart is achieved as C
PControl
charges. An internal grounding switch on the PControl pin
is turned on each time the PFC controller is disabled, and
turned off when it is enabled. This ensures that C
PControl
is
always fully discharged at the beginning of softstart.
As the PFC stage approaches regulation on the output, the
error amplifier output current, I
EA
, gradually reduces to
0 mA. Once the output is in regulation and I
EA
reaches 0 mA,
the IENABLE pin is set to V
IENABLE(high)
(typically 5 V).
V
CC
MANAGEMENT
When power is initially applied to the application, the V
CC
capacitor (C
VCC
) begins charging through a resistor
connected to the high voltage line (V
in
). The resistor value
must be chosen so that the charging current is greater than
the IC bias current during startup. The maximum value for
the startup resistor is calculated using Equation 1.
R
start
+
V
in
I
CC5
(eq. 1)
where V
in
is the rectified dc input voltage and I
CC5
is the IC
bias current during startup (20 mA maximum).
When V
CC
reaches V
CC(reset)
(typically 6.5 V), a Power
On Reset occurs. This resets all logic states on the device. As
V
CC
continues to rise, the IC bias current remains at I
CC5
until V
CC
reaches V
CC(on)
(typically 17 V). Once V
CC
reaches V
CC(on)
, the flyback controller is enabled and the IC
bias current increases to I
CC3
(1.5 mA typical). However,
the total I
CC
current is greater than this due to the gate charge
load at the flyback drive output (FDRV). Once the flyback
is in regulation, the PFC controller can be enabled. When the
PFC is enabled, the I
CC
current increases further due to the
gate charge load at the PFC drive output (PDRV). The
increase in I
CC
per MOSFET is calculated using Equation 2.
I
CC(x)
+ f
OSC
@ Q
G(x)
(eq. 2)
where, f
OSC
is the switching frequency and Q
G(X)
is the gate
charge of the external MOSFET X.
C
VCC
must be sized such that a V
CC
voltage greater than
V
CC(off)
(9 V typical) is maintained while the auxiliary
supply voltage increases during startup. If C
VCC
is too small,
V
CC
falls below V
CC(off)
and the controller turns off before
the auxiliary winding powers up the controller. The total I
CC
current after the flyback controller is enabled (I
CC3
plus
I
CC(FDRV)
) must be considered to correctly size C
VCC
. It is
often useful to connect a small V
CC
capacitor (C1) directly
to the V
CC
pin, while a larger capacitor (C2) is connected to
the V
CC
pin through a diode and charged by the aux winding.
This allows minimum startup time while providing enough
V
CC
capacitance to operate during light load conditions.
This implementation is shown in Figure 3 and the startup
sequence is shown in Figure 4.
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