NCP1927
http://onsemi.com
17
Output Regulation
The NCP1927 error amplifier (EA) consists of an
operational transconductance amplifier (OTA) with the
inverting input connected to the PFB pin and the output
connected to the PControl pin to regulate the output voltage.
It features a typical transconductance (gm) of 200 mS and a
maximum output (I
EA(SRC)
and I
EA(SNK)
) of $20 mA
(typical). The noninverting input is connected internally to
a voltage reference (V
REF
) with a typical value of 2.5 V
$1.5% over process and temperature. During normal
operation, the voltage on the PControl pin varies between
V
PControl(MIN)
  (typically 0.6 V)   and   V
PControl(MAX)
(typically 5.6 V). A simplified diagram of the OTA circuit
is shown in Figure 19.
Figure 19. Error Amplifier and On Time Regulation
Circuits
C
PControl
A resistor divider from the boost output to the PFB pin
provides a scaleddown representation of the output voltage
(V
out
) to the EA. When V
out
is in regulation, V
PFB
equals
V
REF
. If V
out
drops below regulation, the feedback voltage
(V
PFB
) drops and the EA sources current until V
PFB
returns
towards V
REF
. This increases the control voltage (V
PControl
)
and the on time of the driver (t
on
), which in turn increases the
power delivered to the load and brings V
out
back into
regulation. Alternatively, if V
out
(and also V
PFB
) is too high,
the EA sinks current and V
PControl
decreases, thus
shortening t
on
until V
out
returns to regulation. The output
voltage is calculated using Equation 7.
V
out
+ V
REF
@
R
PFB1
) R
PFB2
R
PFB2
(eq. 7)
where R
PFB1
is the upper resistor of the resistor divider, and
R
PFB2
is the lower resistor.
The impedance of the feedback network determines its
noise immunity and power dissipation. While a lower
impedance provides better noise immunity, it also increases
power dissipation. Once the divider current is chosen, R
PFB1
is determined using Equation 8.
R
PFB1
+
V
out
I
divider
(eq. 8)
where I
divider
is the resistor divider current.
Using R
PFB1
, R
PFB2
is calculated with Equation 9.
R
PFB2
+
R
PFB1
@ V
REF
V
out
* V
REF
(eq. 9)
Compensation
A compensation network must be connected between the
PControl pin and ground due to the nature of an active PFC
circuit. The PFC stage generates a sinusoidal current from
the ac line voltage and provides the load with a power that
matches the average demand. When the input voltage is at
its peak, the PFC stage delivers more power than the load
requires, and the output capacitor charges. Conversely,
when the input voltage is at a valley, the load requires more
power than the PFC stage can deliver, and the output
capacitor discharges. The situation is depicted in Figure 20.
Figure 20. Output Voltage Ripple for a Constant
Output Power
time
time
time
V
out
(t)
P
out
(t)
P
in
(t)
V
in
(t)
I
in
(t)
This creates a ripple on the output with frequency equal to
twice the line frequency (f
line
). Since the on time must
remain constant during each ac line cycle to maintain good
power factor correction, the EA must reject the output
ripple. This is commonly achieved by setting the regulation
bandwidth below 20 Hz. A type 1 compensation network is
typically used for simplicity, as it only requires a single
capacitor (C
PControl
) connected between the PControl pin
and ground (see Figure 19). For a type 1 network, C
PControl
is calculated using Equation 10.
C
PControl
+
gm
2p @ f
c
(eq. 10)
where gm is the transconductance of the EA (typically
200 mS), and f
c
is the desired crossover frequency (typically
less than 20 Hz).