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參數(shù)資料
| 型號(hào)： | NM24W03UFLZEN |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | PROM |
| 英文描述： | 256 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 99K |
| 代理商： | NM24W03UFLZEN |
5
www.fairchildsemi.com
NM24C02U/NM24C03U Rev. B.1
NM24C02U/NM24C03U
–
2K-Bit
Serial
EEPROM
2-Wire
Bus
Interface
AC Conditions of Test
Input Pulse Levels
V
CC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10 ns
Input & Output Timing Levels
V
CC x 0.5
Output Load
1 TTL Gate and CL = 100 pF
Read and Write Cycle Limits (Standard and Low V
CC Range)
Symbol
Parameter
100 KHz
400 KHz
Units
Min
Max
Min
Max
fSCL
SCL Clock Frequency
100
400
KHz
T
I
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V
IN
100
50
ns
Pulse width)
t
AA
SCL Low to SDA Data Out Valid
0.3
3.5
0.1
0.9
s
tBUF
Time the Bus Must Be Free before
4.7
1.3
s
a New Transmission Can Start
tHD:STA
Start Condition Hold Time
4.0
0.6
s
t
LOW
Clock Low Period
4.7
1.5
s
tHIGH
Clock High Period
4.0
0.6
s
t
SU:STA
Start Condition Setup Time
4.7
0.6
s
(for a Repeated Start Condition)
t
HD:DAT
Data in Hold Time
0
s
t
SU:DAT
Data in Setup Time
250
100
ns
tR
SDA and SCL Rise Time
1
0.3
s
t
F
SDA and SCL Fall Time
300
ns
tSU:STO
Stop Condition Setup Time
4.7
0.6
s
t
DH
Data Out Hold Time
300
50
ns
tWR
Write Cycle Time - NM24C02U/03U
10
ms
(Note 3)
- NM24C02U/03UL, NM24C02U/03ULZ
15
Note 3: The write cycle time (t
WR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM24C02U/03U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
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