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參數(shù)資料
| 型號： | NT511740D5J-5L |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | 4M X 4 EDO DRAM, 50 ns, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOJ-26/24 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 129K |
| 代理商： | NT511740D5J-5L |
NT511740D5J
16MEG : x4
CMOS with Extended Data Out
REV 1.0 May. 2000
8
NANYA TECHNOLOGY CORP.
NAYNA TECHNOLOGY CORP. reserves the right to change products and specifications without notice.
AC CHARACTERISTICS (Continued )
-50
-60
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
CAS to W delay time
t CWD
30
34
ns
7
RAS to W delay time
t RWD
67
79
ns
7
Column address to W delay time
t AWD
42
49
ns
7
CAS precharge to W delay time
t CPWD
47
54
ns
CAS set-up time ( CAS -before- RAS refresh)
t CSR
5
ns
CAS hold time ( CAS -before- RAS refresh)
t CHR
10
ns
RAS to CAS precharge time
t RPC
5
ns
Access time from CAS precharge
t CPA
28
35
ns
3
Hyper Page cycle time
t HPC
20
25
ns
13
Hyper Page read-modify-write cycle time
t HPRWC
47
56
ns
13
CAS precharge time (Hyper Page cycle)
t CP
7
10
ns
RAS pulse width (Hyper Page cycle)
t RASP
50
100k
60
100k
ns
RAS hold time from CAS precharge
t RHCP
30
35
ns
OE access time
t OEA
13
15
ns
OE to data delay
t OED
12
15
ns
Output buffer turn off delay time from OE
t OEZ
3
ns
6
OE command hold time
t OEH
7
10
ns
Write command set-up time (Test mode in)
t WTS
7
10
ns
11
Write command hold time (Test mode in)
t WTH
10
ns
11
W to RAS precharge time(C-B-R refresh)
t WRP
10
ns
W to RAS hold time(C-B-R refresh)
t WRH
10
ns
Output data hold time
t DOH
5
ns
Output buffer turn off delay from RAS
t REZ
0
ns
6,14
Output buffer turn off delay from W
t WEZ
0
ns
6
W to data delay
t WED
10
ns
OE to CAS hold time
t OCH
5
ns
CAS hold time to OE
t CHO
5
ns
OE precharge time
t OEP
7
10
ns
W pulse width (Hyper Page Cycle)
t WPE
7
10
ns
RAS pulse width (C-B-R self refresh)
t RASS
100
ns
15,16,17
RAS precharge time (C-B-R self refresh)
t RPS
90
110
ns
15,16,17
CAS hold time (C-B-R self refresh)
t CHS
-50
ns
15,16,17
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