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參數(shù)資料
| 型號： | OM13336,598 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT 6 BOARDS DEMO LOGIC |
| 特色產(chǎn)品： | Demo Boards |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 邏輯，二進(jìn)制計數(shù)器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | 74LVC169 |
| 主要屬性： | 1.2 V ~ 3.6 V 輸入電壓 |
| 次要屬性： | 內(nèi)置超前進(jìn)位功能 |
| 已供物品： | 板 |
| 其它名稱： | 568-5082 74LVC169EVB |
74LVC169
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 29 November 2012
2 of 24
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
In order for counting to occur, both pins CEP and CET must be LOW and pin PE must be
HIGH. The pin U/D input determines the direction of the counting. The terminal count
output pin TC output is normally HIGH and goes LOW, provided that pin CET is LOW,
when a counter reaches 15 in the count up mode. The pin TC output state is not a function
of the count-enable parallel (pin CEP) input level. Since pin TC signal is derived by
decoding the flip-flop states, there exists the possibility of decoding spikes on pin TC. For
this reason the use of pin TC as a clock signal is not recommended; see the following
logic equations:
2.
Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Up/down counting
Two count enable inputs for n-bit cascading
Built-in look-ahead carry capability
Presettable for programmable operation
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from
40 Cto+85 C and from 40 Cto+125 C
count enable
CEP
CET
PE
=
count up: TC
Q3
Q2
Q1
Q0
CET
U D
=
count down: TC
Q3
Q2
Q1
Q0
CET
U D
=
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