參數(shù)資料
型號: ATTINY24A-SSU
廠商: Atmel
文件頁數(shù): 3/135頁
文件大?。?/td> 0K
描述: MCU AVR 2K FLASH 20MHZ 14SOIC
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
tinyAVR Introduction
標(biāo)準(zhǔn)包裝: 57
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: USI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 2KB(1K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 管件
配用: ATSTK600-RC46-ND - STK600 ROUTING CARD AVR
ATSTK505-ND - ADAPTER KIT FOR 14PIN AVR MCU
100
32015G–AVR32–09/09
AT32AP7001
11.5.6.2
Supported sleep modes
The following sleep modes are supported. These are detailed in Table 11-2.
Idle: The CPU is stopped, the rest of the chip is operating. Wake-up sources are any interrupt,
or WAKE_N pin.
Frozen: The CPU and HSB modules are stopped, peripherals are operating. Wake-up sources
are any interrupt from PB modules, or WAKE_N pin.
Standby: All synchronous clocks are stopped, but oscillators and PLL’s are running, allowing
quick wake-up to normal mode. Wake-up sources are RTC or external interrupt, or WAKE_N
pin.
Stop: As Standby, but Oscillator 0 and 1, and the PLL’s are stopped. 32 KHz oscillator and
RTC/WDT still operates. Wake-up sources are RTC or external interrupt, or WAKE_N pin.
Static: All oscillators and clocks are stopped. Wake-up sources are external interrupt or
WAKE_N pin.
11.5.6.3
Precautions when entering sleep mode
Modules communicating with external circuits should normally be disabled before entering a
sleep mode that will stop the module operation. This prevents erratic behavior when entering or
exiting sleep mode. Please refer to the relevant module documentation for recommended
actions.
Communication between the synchronous clock domains is disturbed when entering and exiting
sleep modes. This means that bus transactions are not allowed between clock domains affected
by the sleep mode. The system may hang if the bus clocks are stopped in the middle of a bus
transaction.
The CPU and caches are automatically stopped in a safe state to ensure that all CPU bus oper-
ations are complete when the sleep mode goes into effect. Thus, when entering Idle mode, no
further action is necessary.
When entering a deeper sleep mode than Idle mode, all other HSB masters must be stopped
before entering the sleep mode. Also, if there is a chance that any PB write operations are
incomplete, the CPU should perform a read operation from any register on the PB bus before
executing the sleep instruction. This will stall the CPU while waiting for any pending PB opera-
tions to complete.
The Power manager will normally turn of all debug related clocks in the system in the static sleep
mode, m aking it impossible for a debugger to comm unicate with the system . If a
Table 11-2.
Sleep modes
Index
Sleep Mode
CPU
HSB
PBA,B +
GCLK
Osc0,1 +
PLL0,1
Osc32 +
RTC/WDT
0
Idle
Off
On
1
Frozen
Off
OffOnOnOn
2
Standby
Off
On
3
Stop
Off
On
5
Static
Off
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