SBOS342B – DECEMBER 2008 – REVISED AUGUST 2009 ........" />
參數資料
型號: OPA659IDBVT
廠商: Texas Instruments
文件頁數: 8/32頁
文件大?。?/td> 0K
描述: IC OPAMP JFET 650MHZ SGL SOT23-5
標準包裝: 1
放大器類型: J-FET
電路數: 1
轉換速率: 2550 V/µs
增益帶寬積: 350MHz
-3db帶寬: 650MHz
電流 - 輸入偏壓: 10pA
電壓 - 輸入偏移: 1000µV
電流 - 電源: 32mA
電流 - 輸出 / 通道: 70mA
電壓 - 電源,單路/雙路(±): ±3.5 V ~ 6.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SC-74A,SOT-753
供應商設備封裝: SOT-23-5
包裝: 標準包裝
產品目錄頁面: 855 (CN2011-ZH PDF)
其它名稱: 296-24971-6
Driving Capacitive Loads
Distortion Performance
SBOS342B – DECEMBER 2008 – REVISED AUGUST 2009 ............................................................................................................................................ www.ti.com
One of the most demanding, and yet very common,
The OPA659 is capable of delivering a low distortion
load conditions for an op amp is capacitive loading.
signal at high frequencies over a wide range of gains.
The OPA659 is very robust, but care should be taken
The distortion plots in the Typical Characteristics
with
light
loading
scenarios
so
that
output
show the typical distortion under a wide variety of
capacitance does not decrease stability and increase
conditions. Generally, until the fundamental signal
closed-loop frequency response peaking when a
reaches very high frequencies or powers, the second
capacitive load is placed directly on the output pin.
harmonic dominates the distortion with a negligible
When the amplifier open-loop output resistance is
third harmonic component. Focusing then on the
considered,
this
capacitive
load
introduces
an
second harmonic, increasing the load impedance
additional pole in the signal path that can decrease
improves distortion directly. Remember that the total
the phase margin. Several external solutions to this
load
includes
the
feedback
network:
in
the
problem have been suggested. When the primary
noninverting configuration, this network is the sum of
considerations
are
frequency
response
flatness,
RF + RG, while in the inverting configuration the
pulse response fidelity, and/or distortion, the simplest
network is only RF (see Figure 35). Increasing the
and most effective solution is to isolate the capacitive
output voltage swing directly increases harmonic
load from the feedback loop by inserting a series
distortion. A 6dB increase in output swing generally
isolation resistor, RISO, between the amplifier output
increases the second harmonic by 12dB and the third
and the capacitive load. In effect, this resistor isolates
harmonic by 18dB. Increasing the signal gain also
the phase shift from the loop gain of the amplifier,
increases the second-harmonic distortion. Again, a
thus increasing the phase margin and improving
6dB increase in gain increases the second and third
stability.
The
show
the
harmonics by about 6dB, even with a constant output
recommended RISO versus capacitive load and the
power and frequency. Finally, the distortion increases
resulting frequency response with a 1k
load (see
as the fundamental frequency increases because of
Figure 24). Note that larger RISO values are required
the rolloff in the loop gain with frequency. Conversely,
for lower capacitive loading. In this case, a design
the distortion improves going to lower frequencies,
target of a maximally-flat frequency response was
down
to
the
dominant
open-loop
pole
at
used. Lower values of RISO may be used if some
approximately 300kHz.
peaking can be tolerated. Also, operating at higher
Note that power-supply decoupling is critical for
gains (instead of the +1 gain used in the Typical
harmonic distortion performance. In particular, for
Characteristics) requires lower values of RISO for a
optimal
second-harmonic
performance,
the
minimally-peaked
frequency
response.
Parasitic
power-supply
high-frequency
0.1
F
decoupling
capacitive loads greater than 2pF can begin to
capacitors to the positive and negative supply pins
degrade the performance of the OPA659. Moreover,
should be brought to a single point ground located
long PCB traces, unmatched cables, and connections
away from the input pins.
to multiple devices can easily cause this value to be
exceeded. Always consider this effect carefully, and
The OPA659 has an extremely low third-order
add the recommended series resistor as close as
harmonic distortion. This characteristic also shows up
possible to the OPA659 output pin (see the Board
in the two-tone, third-order intermodulation spurious
Layout section).
(IMD3)
response
curves
(see
The
third-order spurious levels are extremely low (less
With heavier loads (for example, the 100
load
than –100dBc) at low output power levels and
presented in the test circuits and used for testing
frequencies
below
10MHz.
The
output
stage
typical characteristic performance), the OPA659 is
continues to hold these levels low even as the
very robust; RISO can be as low as 10 with
fundamental power reaches higher levels. As with
capacitive loads less than 5pF and continue to show
most op amps, the spurious intermodulation powers
a flat frequency response.
do not increase as predicted by a traditional intercept
space
model. As the fundamental power level increases, the
dynamic range does not decrease significantly. For
space
two tones centered at 10MHz, with –2dBm/tone into a
matched 50
load (that is, 0.5VPP for each tone at
the load, which requires 2VPP for the overall two-tone
envelope
at
the
output
pin),
the
Characteristics show a 96dBc difference between the
test
tones
and
the
third-order
intermodulation
spurious
levels.
This
exceptional
performance
improves further when operating at lower frequencies
and/or higher load impedances.
16
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): OPA659
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