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4
TEST AND MEASUREMENT PRODUCTS
www.semtech.com
PE-A2
Optimizing the Output Configuration of
Semtech Bipolar Pin Drivers
Revision 1 / December 18, 2002
Figure 4. External Components for Obtaining DCL AC Performance
46.5
VINP
(or Load)
DUT Pin
DOUT
50
Transmission Line
0805
DCL Part
46.5
40.2
VINP
DUT Pin
LOAD
DOUT
50
Transmission Line
8.2nh
0603
0603
0805
3.3nh
0603
DCL Part
Optimum inductance values will change somewhat
depending on the amount of board parasitic capacitance.
The larger the board parasitics, the larger the inductors
will need to be. Semtech
’
s EVM boards typically use
0.014
”
(0.35mm) thick dielectric in order to minimize the
amount of board parasitic capacitance. If thinner dielectric
is used in order to get thinner 50
transmission line width
(often done to get the high board density), the ground
plane directly beneath the LOAD and VINP pins and the
inductors between the pins can be removed to reduce the
parasitic capacitance. Since the DOUT pin is inductive,
removing the ground plane underneath this pin and the
series resistor will not generally yield much improvement.
For different board parasitic capacitances, approximate
inductor values can be calculated by using the data sheet
values for the comparator and load capacitances (~ 3.5pF
each for the E715C), assuming a Driver inductance of
~ 5nh and using compensation of 2.5nh/pF inductance
for the LOAD pin and VINP pin nodes. If needed, further
refinement of these values can be done after the board is
assembled by measuring the waveform at the DUT pin
using a high-impedance (500
or higher) probe and
increasing or decreasing the inductor values to remove
the overshoot or undershoot as previously shown in
Figure 2. It is important that this be done with the fastest
rise/fall time signals. At slower rise/fall times the effect of
the lumped capacitance will be less making it more difficult
to obtain the ideal values for the higher frequency signals.
On the other hand, once the high-speed signals are
optimized, the lower speed signals will also have their best
performance.
If only the comparator or load is connected to the driver
(but not both), then the inductance of the driver almost
perfectly matches the capacitance of the comparator or
load pin so the optimum circuit does not need any
compensation as shown in Figure 4. If needed, a small
series inductor can be added between the Driver output
and the VINP or LOAD pin to compensate for the board
parasitic capacitance.
If only the driver is connected to the transmission line
without the comparator or load, then the source impedance
will be slightly inductive. To get optimum impedance
matching, a parallel capacitor should be connected as
shown in Figure 6.
Figure 5. External Components for Obtaining Optimum Performance
with Driver-Comparator or Driver-Load Only Connected