參數(shù)資料
型號(hào)： OR2C06A-3S144I
廠商： Electronic Theatre Controls, Inc.
元件分類(lèi)： FPGA
英文描述： Field-Programmable Gate Arrays
中文描述： 現(xiàn)場(chǎng)可編程門(mén)陣列
文件頁(yè)數(shù)： 105/192頁(yè)
文件大小： 3148K
代理商： OR2C06A-3S144I
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)當(dāng)前第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)
Data Sheet
ORCA Series 2 FPGAs
June 1999
2
Lucent Technologies Inc.
Table of Contents
Contents
Page
Contents
Page
Features ...................................................................... 1
Description................................................................... 3
ORCA Foundry Development System Overview......... 5
Architecture ................................................................. 5
Programmable Logic Cells .......................................... 5
Programmable Function Unit ................................... 5
Look-Up Table Operating Modes ............................ 7
Latches/Flip-Flops ................................................. 15
PLC Routing Resources ........................................ 17
PLC Architectural Description................................ 22
Programmable Input/Output Cells ............................. 25
Inputs ..................................................................... 25
Outputs .................................................................. 26
5 V Tolerant I/O (OR2TxxB) .................................. 27
PCI Compliant I/O.................................................. 27
PIC Routing Resources ......................................... 28
PIC Architectural Description................................. 29
PLC-PIC Routing Resources ................................. 30
Interquad Routing ...................................................... 32
Subquad Routing (OR2C40A/OR2T40A Only)...... 34
PIC Interquad (MID) Routing ................................. 36
Programmable Corner Cells ...................................... 37
Programmable Routing.......................................... 37
Special-Purpose Functions.................................... 37
Clock Distribution Network ........................................ 37
Primary Clock ........................................................ 37
Secondary Clock ................................................... 38
Selecting Clock Input Pins ..................................... 39
FPGA States of Operation......................................... 40
Initialization ............................................................ 40
Configuration ......................................................... 41
Start-Up ................................................................. 42
Reconfiguration ..................................................... 42
Partial Reconfiguration .......................................... 43
Other Configuration Options .................................. 43
Configuration Data Format ........................................ 43
Using
ORCA Foundry to Generate
Configuration RAM Data..................................... 44
Configuration Data Frame ..................................... 44
Bit Stream Error Checking......................................... 47
FPGA Configuration Modes....................................... 47
Master Parallel Mode............................................. 47
Master Serial Mode ............................................... 48
Asynchronous Peripheral Mode ............................ 49
Synchronous Peripheral Mode .............................. 49
Slave Serial Mode ................................................. 50
Slave Parallel Mode............................................... 50
Daisy Chain ........................................................... 51
Special Function Blocks ............................................ 52
Single Function Blocks .......................................... 52
Boundary Scan ...................................................... 54
Boundary-Scan Instructions...................................55
ORCA Boundary-Scan Circuitry ............................56
ORCA Timing Characteristics....................................60
Estimating Power Dissipation ....................................61
OR2CxxA...............................................................61
OR2TxxA ...............................................................63
OR2T15B and OR2T40B .......................................65
Pin Information ..........................................................66
Pin Descriptions.....................................................66
Package Compatibility ...........................................68
Compatibility with Series 3 FPGAs ........................70
Package Thermal Characteristics............................126
QJA ......................................................................126
yJC.......................................................................126
QJC......................................................................126
QJB......................................................................126
Package Coplanarity ...............................................127
Package Parasitics ..................................................127
Absolute Maximum Ratings .....................................129
Recommended Operating Conditions......................129
Electrical Characteristics .........................................130
Timing Characteristics .............................................132
Series 2................................................................160
Measurement Conditions.........................................169
Output Buffer Characteristics...................................170
OR2CxxA.............................................................170
OR2TxxA .............................................................171
OR2TxxB .............................................................172
Package Outline Drawings ......................................173
Terms and Definitions ..........................................173
84-Pin PLCC........................................................174
100-Pin TQFP ......................................................175
144-Pin TQFP ......................................................176
160-Pin QFP ........................................................177
208-Pin SQFP......................................................178
208-Pin SQFP2....................................................179
240-Pin SQFP......................................................180
240-Pin SQFP2....................................................181
256-Pin PBGA .....................................................182
304-Pin SQFP......................................................183
304-Pin SQFP2....................................................184
352-Pin PBGA .....................................................185
432-Pin EBGA .....................................................186
Ordering Information................................................187
Index ........................................................................189
相關(guān)PDF資料
PDF描述
OR2C06A-3S160 Field-Programmable Gate Arrays
OR2C06A-3S160I Field-Programmable Gate Arrays
OR2C06A-3S208 Field-Programmable Gate Arrays
OR2C06A-3S208I Field-Programmable Gate Arrays
OR2C06A-3S240 Field-Programmable Gate Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR2C06A-3S160 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Gate Arrays
OR2C06A-3S160I 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Gate Arrays
OR2C06A-3S208 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Gate Arrays
OR2C06A-3S208I 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Gate Arrays
OR2C06A3S208I-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*