參數(shù)資料
型號： ORLI10G3BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁數(shù)： 34/78頁
文件大小： 1689K
代理商： ORLI10G3BM680-DB
Lattice Semiconductor
ORCA ORLI10G Data Sheet
4
420 MHz. Multiplication of input frequency up to 64x and division of input frequency down to 1/64x is possible.
New cycle stealing capability allows a typical 15% to 40% internal speed improvement after nal place and route.
This feature also supports compliance with many setup/hold and clock-to-out I/O specications, and may provide
reduced ground bounce for output buses by allowing exible delays of switching output buffers.
Programmable Logic System Features
PCI local bus compliant for FPGA I/Os.
Improved PowerPC
/PowerQUICC 860, and PowerPC/PowerQUICC II MPC8260 high-speed synchronous
microprocessor interface can be used for conguration, readback, device control, and device status, as well as
for a general-purpose interface to the FPGA logic, RAMs, and embedded standard-cell blocks. Glueless interface
to synchronous PowerPC processors with user-congurable address space is provided.
New embedded AMBA specication 2.0 AHB system bus (ARM
processor) facilitates communication among
the microprocessor interface, conguration logic, embedded block RAM, FPGA logic, and embedded standard
cell blocks.
Variable-size bused readback of conguration data capability with the built-in microprocessor interface and sys-
tem bus.
Internal, 3-state, and bidirectional buses with simple control provided by the SLIC.
New clock routing structures for global and local clocking signicantly increases speed and reduces skew (<200
ps for OR4E04).
New local clock routing structures allow creation of localized clock trees.
Two new edge clock structures allow up to six highspeed clocks on each edge of the device for improved
setup/hold and clock-to-out performance.
New Double-Data Rate (DDR) and Zero-Bus Turn-around (ZBT) memory interfaces support the latest high-
speed memory interfaces.
New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced-speed internal
logic.
ispLEVER development system software. Supported by industry-standard CAE tools for design entry, synthesis,
simulation, and timing analysis.
Meets Universal Test and Operations PHY Interface for ATM (UTOPIA) Levels 1, 2, and 3 as well as POS-PHY3.
Also meets proposed specications for UTOPIA Level 4 and POS-PHY4 for 10 Gbits/s interfaces.
Meets POS-PHY3 (2.5 Gbits/s) and POS-PHY4 (10 Gbits/s) interface standards for packet-over-SONET as
dened by the Saturn Group.
相關PDF資料
PDF描述
ORT82G5-1BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORT82G5-2BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
ORT82G5-3BM680 FPGA, 1296 CLBS, 380000 GATES, PBGA680
OS10040280G-012 FIBER OPTIC RECEIVER, 1290-1600nm, PANEL MOUNT, FC/APC CONNECTOR
OT-WBSC-Y-A-10-X-9-M-3-05-FA FIBER OPTIC SPLITTER/COUPLER, 1X2PORT, 10.0, PANEL MOUNT, FC/APC CONNECTOR
相關代理商/技術參數(shù)
參數(shù)描述
ORLI10G-3BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G5-FPSC-EV 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORLI10G5 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORM0200-03600 N-70 制造商:SMC Corporation of America 功能描述:O-RING
ORM120A110 制造商:Ssac 功能描述:
ORMC615-04 制造商:ORTRONICS 功能描述:ORTRONICS: 15FT, CAT 6 JUMPERS, YELLOW
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