參數(shù)資料
型號： ORT82G5-2BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 38/110頁
文件大小： 1459K
代理商： ORT82G5-2BM680
Lattice Semiconductor
33
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Backplane Transceiver Core Detailed
Description (continued)
Table 10.
Definition of Bits of MRWDxy[39:0]
The use of the FIFO is controlled by conguration bits,
and the raw demultiplexed data can also be sent to the
FPGA directly, by passing the alignment FIFO. The
control register bits for alignment FIFO in ORT82G5
are described below.
Table 11. Multichannel Alignment Modes
Note: Where xx is one of A[A:D] and B[A:D].
To align all eight channels:
■
FMPU_SYNMODE_A[A:D] = 11
■
FMPU_SYNMODE_B[A:D] = 11
To align all four channels in SERDES A:
■
FMPU_SYNMODE_A[A:D] = 01
To align two channels in SERDES A:
■
FMPU_SYNMODE_A[A:B] = 10 for channel AA and
AB
■
FMPU_SYNMODE_A[C:D] = 10 for channel AC and
AD
Similar alignment can be dened for SERDES B.
To enable/disable synchronization signal of individual
channel within a multi-channel alignment group:
■
FMPU_STR_EN_xx = 1 enabled
■
FMPU_STR_EN_xx = 0 disabled
where xx is one of A[A:D] and B[A:D].
Bit Index
NOCHALGNx = 1
NOCHALGNx = 0
39
b9 of char 1
CH248_SYNCx
38
b8 of char 1
K_CTRL for char 1
37
b7 of char 1
36
b6 of char 1
35
b5 of char 1
34
b4 of char 1
33
b3 of char 1
32
b2 of char 1
31
b1 of char 1
30
b0 of char 1
29
b9 of char 2
n/c
28
b8 of char 2
K_CTRL for char 2
27
b7 of char 2
26
b6 of char 2
25
b5 of char 2
24
b4 of char 2
23
b3 of char 2
22
b2 of char 2
21
b1 of char 2
20
b0 of char 2
19
b9 of char 3
n/c
18
b8 of char 3
K_CTRL for char 3
17
b7 of char 3
16
b6 of char 3
15
b5 of char 3
14
b4 of char 3
13
b3 of char 3
12
b2 of char 3
11
b1 of char 3
10
b0 of char 3
09
b9 of char 4
n/c
08
b8 of char 4
K_CTRL for char 4
07
b7 of char 4
06
b6 of char 4
05
b5 of char 4
04
b4 of char 4
03
b3 of char 4
02
b2 of char 4
01
b1 of char 4
00
b0 of char 4
Register Bits
FMPU_SYNMODE_xx
[0:1]
Mode
00
No multichannel alignment.
10
Twin channel alignment.
01
Quad channel alignment.
11
Eight channel alignment.
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ORT82G5-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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