參數(shù)資料
型號： ORT82G5-2BM680
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 380000 GATES, PBGA680
封裝： PLASTIC, BGA-680
文件頁數(shù)： 95/110頁
文件大小： 1459K
代理商： ORT82G5-2BM680
Lattice Semiconductor
85
Data Sheet
January 25, 2002
8b/10b SERDES Backplane Interface FPSC
ORCA ORT82G5 1.0-1.25/2.0-2.5/3.125-3.5 Gbits/s
Pin Information (continued)
Table 32. Embedded Core/FPGA Interface Signal Description (continued)
Pin Name
I/O
Description
Receive Path Signals
MRWDAA[39:0]
O
Receive data—SERDES A, channel A.
MRWDAB[39:0]
O
Receive data—SERDES A, channel B.
MRWDAC[39:0]
O
Receive data—SERDES A, channel C.
MRWDAD[39:0]
O
Receive data—SERDES A, channel D.
MRWDBA[39:0]
O
Receive data—SERDES B, channel A.
MRWDBB[39:0]
O
Receive data—SERDES B, channel B.
MRWDBC[39:0]
O
Receive data—SERDES B, channel C.
MRWDBD[39:0]
O
Receive data—SERDES B, channel D.
RWCKAA
O
Low-speed receive clock—SERDES A, channel A.
RWCKAB
O
Low-speed receive clock—SERDES A, channel B.
RWCKAC
O
Low-speed receive clock—SERDES A, channel C.
RWCKAD
O
Low-speed receive clock—SERDES A, channel D.
RWCKBA
O
Low-speed receive clock—SERDES B, channel A.
RWCKBB
O
Low-speed receive clock—SERDES B, channel B.
RWCKBC
O
Low-speed receive clock—SERDES B, channel C.
RWCKBD
O
Low-speed receive clock—SERDES B, channel D.
RCK78A
O
Receive low-speed clock to FPGA—SERDES A.
RCK78B
O
Receive low-speed clock to FPGA—SERDES B.
RSYS_CLK_A1
I
Low-speed receive FIFO clock for channels AA, AB—SERDES A.
RSYS_CLK_A2
I
Low-speed receive FIFO clock for channels AC, AD—SERDES A.
RSYS_CLK_B1
I
Low-speed receive FIFO clock for channels BA, BB—SERDES B.
RSYS_CLK_B2
I
Low-speed receive FIFO clock for channels BC, BD—SERDES B
SYS_RST_N
I
Synchronous reset of the channel alignment blocks.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORT82G5-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2F680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT82G5-2FN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 1.5V 3.7 G b Bpln Xcvr 643K Gt RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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