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參數(shù)資料
| 型號： | OX16PCI952-TQFP-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁數(shù)： | 47/76頁 |
| 文件大小： | 1386K |
| 代理商： | OX16PCI952-TQFP-A |
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ASR[4]: Special character detected
logic 0
No special character has been detected.
logic 1
A special character has been received and is
stored in the RHR.
This can be used to determne whether a level 5 interrupt
was caused by receiving a special character rather than an
XOFF. The flag is cleared following the read of the ASR.
ASR[5]: FIFOSEL
This bit reflects the unlatched state of the FIFOSEL pin.
ASR[6]: FIFO size
logic 0
FIFOs are 16 deep if FCR[0] = 1.
logic 1
FIFOs are 128 deep if FCR[0] = 1.
ASR[7]: Transmitter Idle
logic 0
Transmtter is transmtting.
logic 1
Transmtter is idle.
This bit reflects the state of the internal transmtter. It is set
when both the transmtter FIFO and shift register are
empty.
7.11.2 FIFO Fill levels ‘TFL & RFL’
The number of characters stored in the THR and RHR can
be determned by reading the TFL and RFL registers
respectively. When data transfer is in constant operation,
the values should be interpreted as follows:
1. The number of characters in the THR is no greater
than the value read back fromTFL.
2. The number of characters in the RHR is no less than
the value read back fromRFL.
7.11.3 Additional Control Register ‘ACR’
The ACR register is located at offset 0x00 of the ICR
ACR[0]: Receiver disable
logic 0
The receiver is enabled, receiving data and
storing it in the RHR.
logic 1
The receiver is disabled. The receiver
continues to operate as normal to maintain the
framng synchronisation with the receive data
streambut received data is not stored into the
RHR. In-band flow control characters continue
to be detected and acted upon. Special
characters will not be detected.
Changes to this bit will only be recognised following the
completion ofany data reception pending.
DataSheet Revision 1.1
Page 47
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
ACR[1]: Transmitter disable
logic 0
The transmtter is enabled, transmtting any
data in the THR.
logic 1
The transmtter is disabled. Any data in the
THR is not transmtted but is held. However, in-
band flow control characters may still be
transmtted.
Changes to this bit will only be recognised following the
completion of any data transmssion pending.
ACR[2]: Enable automatic DSR flow control
logic 0
Normal. The state of the DSR#line does not
affect the flow control.
logic 1
Data transmssion is prevented whenever the
DSR#pin is held inactive high.
This bit provides another automatic outof-band flow control
facility using the DSR#line.
ACR[4:3]: DTR# line configuration
When bits 4 or 5 of CKS (offset 0x03 of ICR) are set, the
transmtter 1x clock or the output of the baud rate
generator (Nx clock) are asserted on the DTR#pin,
otherwise the DTR#pin is defined as follows:
logic [00]
DTR# is compatible with 16C450, 16C550,
16C650 and 16C750 (i.e. normal).
logic [01]
DTR# pin is used for outof-band flow control.
It will be forced inactive high if the Receiver
FIFO Level (‘RFL’) reaches the upper flow
control threshold. DTR# line will be re-
activated (=0) when the RFL drops below the
lower threshold (see FCL & FCH).
logic [10]
DTR# pin is configured to drive the active-low
enable pin of an external RS485 buffer. In
this configuration the DTR#pin will be forced
low whenever the transmtter is not empty
(LSR[6]=0), otherwise DTR# pin is high.
logic [11]
DTR#pin is configured to drive the active-
high enable pin of an external RS485 buffer.
In this configuration, the DTR# pin will be
forced high whenever the transmtter is not
empty (LSR[6]=0), otherwise DTR#pin is low.
If the user sets ACR[4], then the DTR# line is controlled by
the status of the transmtter empty bit of LCR. When
ACR[4] is set, ACR[3] is used to select active high or active
low enable signals. In halfduplex systems using RS485
protocol, this facility enables the DTR#line to directly
control the enable signal of external 3-state line driver
buffers. When the transmtter is empty the DTR#would go
inactive once the SOUT line returns to it’s idle marking
state.
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