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參數(shù)資料
| 型號： | OX16PCI952-TQFP-A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface |
| 中文描述： | 集成高性能的雙UART，并行端口和5.0V PCI接口 |
| 文件頁數(shù)： | 63/76頁 |
| 文件大?。?/td> | 1386K |
| 代理商： | OX16PCI952-TQFP-A |
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12 AC ELECTRICAL CHARACTERISTICS
DataSheet Revision 1.1
Page 63
OX16PCI952
OXFORD SEMICONDUCTOR LTD.
12.1 PCI I/O Buffers
All PCI I/O buffers are compliant to the AC Electrical Characteristics of the 5.0v signalling environment, as defined in the
PCI Local Bus Specification, revision 2.2. (Section 4.2.1.2 of this specification)
AC Specifications
Switching current
0 < V
OUT
1.4
I
OH(AC)
high
1.4 < V
OUT
2.4
3.1 < V
OUT
V
CC
(Test point)
V
OUT
= 3.1
Switching current
V
OUT
2.2
I
OL(AC)
low
2.2 > V
OUT
> 0.55
0.71 > V
OUT
> 0
(Test point)
V
OUT
= 0.71
I
CL
Low clamp current
-5 < V
IN
< -1
-44
-44 (V
OUT
- 1.4)/0.024
95
V
OUT
/ 0.023
-25 + (V
IN
+1)/
0.015
25+ (V
IN
-V
CC
-1)/
0.015
1
1
mA
mA
mA
Eq. A
-142
Eq. B
206
I
HL
High clamp current
V
CC
+4 < V
IN
<
V
CC
+1
0.4V to 2.4V
2.4V to 0.4V
mA
Slew
R
Slew
F
Output rise slew rate
Output fall slew rate
5
5
V/nS
V/nS
Table 32: Characteristics of PCI I/O buffers
Eq. A :
Eq. B :
I
OH
= 11.9 *(V
OUT
- 5.25) *(V
OUT
+ 2.45)
I
OL
= 78.5 *V
OUT
*(4.4 - V
OUT
)
for 3.1 < V
OUT
V
CC
for 0.71 > V
OUT
> 0
12.2 Serial Ports
Isochronous (x1 Clock) Timing:
Symbol
Parameter
t
irs
SIN setup time to Isochronous input clock ‘Rx_Clk_In rising
1
t
irh
SIN hold time after Isochronous input clock ‘Rx_Clk_In rising
1
t
its
SOUT valid after Isochronous output clock ‘Tx_Clk_Out’ falling
1
Min
TBD
TBD
TBD
Max
10
0.1
6
Units
ns
ns
ns
Table 33: Isochronous mode timing
Note 1:
x1 clock. The systemdesigner is should ensure that mark-to-space ratio of the x1 clock is such that the required set-up and hold timng constraint are met. One
way of achieving this is to choose a crystal frequency which is twice the required data rate and then divide the clock by two using the onboard prescaler. In this
case the mark-to-space ratio is 50/50 for the purpose of set-up and hold calculations.
In Isochronous mode, transmtter data is available after the falling edge of the x1 clock and the receiver data is sampled using the rising edge of the
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