參數(shù)資料
型號(hào): P11976EJ2V0AN00
英文描述: uPC2711-15. uPC2745-49. uPC2791/92. uPC3210 6-Pin Mini-Mold. 6-Pin Super Mini-Mold Silicon High-Frequency Wideband Amplifier MMIC
中文描述: uPC2711 - 15。 uPC2745 - 49。 uPC2791/92。 uPC3210 6引腳小型模具。 6引腳超小型模具硅高頻寬帶放大器單片
文件頁數(shù): 13/31頁
文件大?。?/td> 174K
代理商: P11976EJ2V0AN00
Application Note P11976EJ2V0AN00
13
3.3 Description of Test Circuit
Our measurement method for the electrical specifications listed in the data sheets confirms across a wide band the
characteristics of ICs with minimal signal line effects (such as jigs, etc.). Our measurement method and the PCB are
described below.
Measurement method
Common conditions
A network analyzer is used for the following items
Power gain
Isolation
Input return loss
Output return loss
For other items, the characteristics are rated based frequency conditions set to minimize jig effects.
An NF (Noise Figure) meter is used for the following item
Noise figure
Although this NF contains jigs, frequency conditions are set to minimize
such jigs effects (with compensation for cable loss).
A signal generator and spectrum analyzer are used for the following item
Input/output level characteristics
Although these characteristics contain jigs of the DC cut capacitor,
frequency conditions are set to minimize such jigs effects (with
compensation for cable loss).
PCB
Loss can be reduced depending on the type of PCB. NEC employs a polyimide double-sided PCB on the
test circuit to maximize the performance of the IC itself.
Use through holes to ensure proper grounding.
Make the input/output lines straight to facilitate jig calibration.
Specification
PCB dimensions: 30
×
30
×
0.4 (mm), with 35-
μ
m thick copper patterning on both sides
42
×
35
×
0.4 (mm), with 18-
μ
m thick copper patterning on both sides
(
μ
PC3210 only)
Cut the pattern when inserting a DC cut capacitor.
A feed-through capacitor is used for the bypass capacitor
S
21
of IC with compensation for effect of jigs on input/output lines
S
12
of IC with compensation for effect of jigs on input/output lines
S
11
of IC with compensation for effect of jigs on input/output lines
S
22
of IC with compensation for effect of jigs on input/output lines
Figure 3-2 shows a test circuit and Figures 3-3 to 3-6 show the PCB layout. Before designing actual product
applications, the user should first gain an understanding of the NEC data sheet ratings and measurement data for the
above conditions as well as how characteristics may vary due to the external circuit constants and PCB patterns in
the user set.
Figure 3-2. Test Circuit
DUT
GND
V
CC
Z
L
= 50
Power supply
DC cable
1000 pF (Jig feed-through capacitor)
V
CC
line
Measurement equipment
Measurement equipment
High-frequency
cable
High-frequency
cable
DC cut
DC cut
Input
Output
Z
S
= 50
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