參數(shù)資料
型號(hào)： P80C51FA
廠商： NXP Semiconductors N.V.
英文描述： 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless. low voltage 2.7V-5.5V). low power. high speed (33 MHz)
中文描述： 80C51的8位單片機(jī)系列8K-64K/256-1K檢察官辦公室/光盤/無ROM。低電壓為2.7V至5.5V）。低功耗。高速（33兆赫）
文件頁數(shù)： 15/38頁
文件大?。?/td> 350K
代理商： P80C51FA
Philips Semiconductors
Product specification
80C51/87C51/80C31
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Jan 20
15
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are trended
as don’t-cares. In most cases, interpreting the don’t-cares as ones,
the broadcast address will be FF hexadecimal.
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are leaded with 0s. This produces a given address
of all “don’t cares” as well as a Broadcast address of all “don’t
cares”. This effectively disables the Automatic Addressing mode and
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.
SCON
Address = 98H
Reset Value = 0000 0000B
SM0/FE
7
SM1
6
SM2
5
REN
4
TB8
3
RB8
2
Tl
1
Rl
0
Bit Addressable
(SMOD0 = 0/1)*
Symbol
Function
FE
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0
SM1
Mode
Description
Baud Rate**
0
0
0
shift register
f
OSC
/12
0
1
1
8-bit UART
variable
1
0
2
9-bit UART
f
OSC
/64 or f
OSC
/32
1
1
3
9-bit UART
variable
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
SM0
SM1
SM2
REN
TB8
RB8
Tl
Rl
NOTE:
*SMOD0 is located at PCON6.
**f
OSC
= oscillator frequency
SU00043
Bit:
Figure 7. SCON: Serial Port Control Register
相關(guān)PDF資料
PDF描述
P80C54SFA 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless. low voltage 2.7V-5.5V). low power. high speed (33 MHz)
P80C51FA-4B 80C51 8-bit microcontroller family 8K.64K/256.1K OTP/ROM/ROMless, low voltage 2.7V.5.5V, low power, high speed 33 MHz
P80C51FA-5A 80C51 8-bit microcontroller family 8K.64K/256.1K OTP/ROM/ROMless, low voltage 2.7V.5.5V, low power, high speed 33 MHz
P80C51SBBB 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless low voltage 2.7V.5.5V, low power, high speed 33 MHz
P80C31SBBB 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless low voltage 2.7V.5.5V, low power, high speed 33 MHz
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