參數(shù)資料
型號： P80C51FA
廠商： NXP Semiconductors N.V.
英文描述： 80C51 8-bit microcontroller family 8K-64K/256-1K OTP/ROM/ROMless. low voltage 2.7V-5.5V). low power. high speed (33 MHz)
中文描述： 80C51的8位單片機系列8K-64K/256-1K檢察官辦公室/光盤/無ROM。低電壓為2.7V至5.5V）。低功耗。高速（33兆赫）
文件頁數(shù)： 21/38頁
文件大?。?/td> 350K
代理商： P80C51FA
Philips Semiconductors
Product specification
80C51/87C51/80C31
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Jan 20
21
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C or –40
°
C to +85
°
C, V
CC
= 2.7V to 5.5V, V
SS
= 0V (16MHz devices)
SYMBOL
PARAMETER
TEST
LIMITS
TYP
1
UNIT
CONDITIONS
MIN
MAX
V
IL
Input low voltage
4.0V < V
CC
< 5.5V
2.7V<V
CC
< 4.0V
–0.5
0.2V
CC
–0.1
0.7
V
–0.5
V
V
IH
V
IH1
Input high voltage (ports 0, 1, 2, 3, EA)
0.2V
CC
+0.9
0.7V
CC
V
CC
+0.5
V
CC
+0.5
V
Input high voltage, XTAL1, RST
V
V
OL
Output low voltage, ports 1, 2,
8
V
CC
= 2.7V
I
OL
= 1.6mA
2
V
CC
= 2.7V
I
OL
= 3.2mA
2
V
CC
= 2.7V
I
OH
= –20
μ
A
V
CC
= 4.5V
I
OH
= –30
μ
A
V
CC
= 2.7V
I
OH
= –3.2mA
V
IN
= 0.4V
V
= 2.0V
See note 4
0.4
V
V
OL1
Output low voltage, port 0, ALE, PSEN
8, 7
0.4
V
V
OH
Output high voltage ports 1 2 3
Output high voltage, ports 1, 2, 3
3
V
CC
– 0.7
V
V
CC
– 0.7
V
V
OH1
Output high voltage (port 0 in external bus mode),
ALE
9
, PSEN
3
V
CC
– 0.7
V
I
IL
Logical 0 input current, ports 1, 2, 3
–1
–50
μ
A
I
TL
Logical 1-to-0 transition current, ports 1, 2, 3
6
–650
μ
A
I
LI
I
CC
Input leakage current, port 0
0.45 < V
IN
< V
CC
– 0.3
See note 5
±
10
μ
A
Power supply current (see Figure 21):
Active mode @ 16MHz
Idle mode @ 16MHz
Power-down mode or clock stopped (see Figure 25
for conditions)
μ
A
μ
A
μ
A
μ
A
T
amb
= 0
°
C to 70
°
C
T
amb
= –40
°
C to +85
°
C
3
50
75
R
RST
C
IO
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
s of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
OL
can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the V
CC
–0.7 specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
IN
is approximately 2V.
5. See Figures 22 through 25 for I
CC
test conditions.
Active mode:
I
CC
= 0.9
×
FREQ. + 1.1mA
Idle mode:
I
CC
= 0.18
×
FREQ. +1.01mA; See Figure 21.
6. This value applies to T
amb
= 0
°
C to +70
°
C. For T
amb
= –40
°
C to +85
°
C, I
TL
= –750
μ
A.
7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
8. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin:
15mA (*NOTE: This is 85
°
C specification.)
Maximum I
OL
per 8-bit port:
26mA
Maximum total I
OL
for all outputs:
71mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. ALE is tested to V
OH1
, except when ALE is off then V
OH
is the voltage specification.
10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF
(except EA is 25pF).
Internal reset pull-down resistor
Pin capacitance
10
(except EA)
40
225
k
15
pF
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