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參數(shù)資料
| 型號(hào)： | P80CE598FHB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit microcontroller with CAN controller(帶CAN控制器的8位微控制器) |
| 中文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 20/108頁 |
| 文件大?。?/td> | 661K |
| 代理商： | P80CE598FHB |
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1996 Jun 27
20
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
10.1
ADC Control register (ADCON)
Table 13
ADC Control register (address C5H)
Table 14
Description of the ADCON bits
Table 15
ADCI and ADCS operating modes
If ADCI is cleared by software while ADCS is set at the same time a new analog-to-digital conversion with the same
channel-number may be started. It is recommended to reset ADCI before ADCS is set.
Note
1.
Start of a new conversion requires ADCI = 0.
7
6
5
4
3
2
1
0
ADC.1
ADC.0
ADEX
ADCI
ADCS
AADR2
AADR1
AADR0
BIT
SYMBOL
FUNCTION
7
6
5
ADC.1
ADC.0
ADEX
Bit 1 of ADC converted value.
Bit 0 of ADC converted value.
Enable external start of conversion by STADC. If ADEX is:
LOW, then conversion cannot be started externally by STADC (only by software by
setting ADCS)
HIGH, then conversion can be started externally by a rising edge on STADC or
externally.
ADC interrupt flag.
This flag is set when an analog-to-digital conversion result is ready
to be read.
If enabled, an interrupt is invoked. The flag must be cleared by software.
It cannot be set by software (see Table 15).
ADC start and status.
Setting this bit starts an analog-to-digital conversion. It may be
set by software or by the external signal STADC. The ADC logic ensures that this signal
is HIGH while the ADC is busy. On completion of the conversion, ADCS is reset at the
same time the interrupt flag ADCI is set. ADCS can not be reset by software (see
Table 15).
Analog input select
. This binary coded address selects one of the eight analog port
pins of P5 to be input to the converter. It can only be changed when ADCI and ADCS
are both LOW. AADR2 is the MSB (e.g. 100B selects the analog input channel ADC4).
4
ADCI
3
ADCS
2
1
0
AADR2
AADR1
AADR0
ADCI
ADCS
OPERATION
0
0
1
0
1
ADC not busy, a conversion can be started.
ADC busy, start of a new conversion is blocked.
Conversion completed (note 1).
X (don’t care)
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