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參數(shù)資料
| 型號： | P80CL51 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low voltage 8-bit microcontrollers with UART |
| 中文描述： | 低電壓的8位微控制器的UART的 |
| 文件頁數(shù)： | 12/68頁 |
| 文件大?。?/td> | 305K |
| 代理商： | P80CL51 |
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1997 Apr 15
12
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART
P80CL31; P80CL51
9
MEMORY ORGANIZATION
The P80CLx1 has 4 kbytes of Program Memory (ROM;
P80CL51 only) plus 128 bytes of Data Memory (RAM) on
board.The device has separate address spaces for
Program and Data Memory (see Fig.5). Using Port latches
P0 and P2, the P80CLx1 can address a maximum of
64 kbytes of program memory and a maximum of
64 kbytes of data memory. The CPU generates both read
(RD) and write (WR) signals for external Data Memory
accesses, and the read strobe (PSEN) for external
Program Memory.
9.1
Program Memory
The P80CL51 contains 4 kbytes of internal ROM. After
reset the CPU begins execution at location 0000H.
The lower 4 kbytes of Program Memory can be
implemented in either on-chip ROM or external Program
Memory.
If the EA pin is tied to V
DD
, then Program Memory fetches
from addresses 0000H to 0FFFH are directed to the
internal ROM. Fetches from addresses 1000H to FFFFH
are directed to external ROM. Program Counter values
greater than 0FFFH are automatically addressed to
external memory regardless of the state of the EA pin.
9.2
Data Memory
The P80CLx1 contains 128 bytes of internal RAM and 25
Special Function Registers (SFR). The memory map
(Fig.5) shows the internal Data Memory space divided into
the lower 128, the upper 128, and the SFR space.
The lower 128 bytes of the internal RAM are organized as
mapped in Fig.6. The lowest 32 bytes are grouped into 4
banks of 8 registers. Program instructions refer to these
registers within a register bank as R0 through R7. Two bits
in the Program Status Word select which register bank is
in use. The next 16 bytes above the register banks form a
block of bit-addressable memory space. The 128 bits in
this area can be directly addressed by the single-bit
manipulation instructions. The remaining registers
(30H to 7FH) are directly and indirectly byte addressable.
Fig.5 Memory map.
handbook, full pagewidth
MLA559
INTERNAL
DATA RAM
255
127
0
EXTERNAL
(EA = 0)
INTERNAL
(EA = 1)
INTERNAL DATA MEMORY
EXTERNAL
DATA MEMORY
PROGRAM MEMORY
EXTERNAL
64K
64K
4096
4095
OVERLAPPED SPACE
0
4095
SPECIAL
FUNCTION
REGISTERS
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