- 您現(xiàn)在的位置：買賣IC網 > PDF目錄3798 > P87C52X2BN,112 (NXP Semiconductors)IC 80C51 MCU 8K OTP 40-DIP PDF資料下載
參數資料
| 型號： | P87C52X2BN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 29/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU 8K OTP 40-DIP |
| 產品培訓模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標準包裝： | 9 |
| 系列： | 87C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，UART/USART |
| 外圍設備： | POR |
| 輸入/輸出數： | 32 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 內部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
| 產品目錄頁面： | 705 (CN2011-ZH PDF) |
| 其它名稱： | 568-1013-5 935269601112 P87C52X2BN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁
Philips Semiconductors
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
2003 Jan 24
35
. . . .
C1
C2
C3
C4
C5
. . . .
Interrupts
Are Polled
Long Call to
Interrupt
Vector Address
Interrupt Routine
ε
Interrupt
Goes
Active
. . . . . . . . .
Interrupt
Latched
This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP.
S5P2
S6
. . . . . . . . .
SU00546
Figure 25. Interrupt Response Timing Diagram
The polling cycle/LCALL sequence is illustrated in Figure 25.
Note that if an interrupt of higher priority level goes active prior to
S5P2 of the machine cycle labeled C3 in Figure 25, then in
accordance with the above rules it will be vectored to during C5 and
C6, without any instruction of the lower priority routine having been
executed.
Thus the processor acknowledges an interrupt request by executing
a hardware-generated LCALL to the appropriate servicing routine. In
some cases it also clears the flag that generated the interrupt, and in
other cases it doesn’t. It never clears the Serial Port flag. This has to
be done in the user’s software. It clears an external interrupt flag
(IE0 or IE1) only if it was transition-activated. The
hardware-generated LCALL pushes the contents of the Program
Counter on to the stack (but it does not save the PSW) and reloads
the PC with an address that depends on the source of the interrupt
being vectored to, as shown in Table 8.
Execution proceeds from that location until the RETI instruction is
encountered. The RETI instruction informs the processor that this
interrupt routine is no longer in progress, then pops the top two
bytes from the stack and reloads the Program Counter. Execution of
the interrupted program continues from where it left off.
Note that a simple RET instruction would also have returned
execution to the interrupted program, but it would have left the
interrupt control system thinking an interrupt was still in progress,
making future interrupts impossible.
External Interrupts
The external sources can be programmed to be level-activated or
transition-activated by setting or clearing bit IT1 or IT0 in Register
TCON. If ITx = 0, external interrupt x is triggered by a detected low
at the INTx pin. If ITx = 1, external interrupt x is edge triggered. In
this mode if successive samples of the INTx pin show a high in one
cycle and a low in the next cycle, interrupt request flag IEx in TCON
is set. Flag bit IEx then requests the interrupt.
Since the external interrupt pins are sampled once each machine
cycle, an input high or low should hold for at least 12 oscillator
periods to ensure sampling. If the external interrupt is
transition-activated, the external source has to hold the request pin
high for at least one cycle, and then hold it low for at least one cycle.
This is done to ensure that the transition is seen so that interrupt
request flag IEx will be set. IEx will be automatically cleared by the
CPU when the service routine is called.
If the external interrupt is level-activated, the external source has to
hold the request active until the requested interrupt is actually
generated. Then it has to deactivate the request before the interrupt
service routine is completed, or else another interrupt will be
generated.
Response Time
The INT0 and INT1 levels are inverted and latched into IE0 and IE1
at S5P2 of every machine cycle. The values are not actually polled
by the circuitry until the next machine cycle. If a request is active
and conditions are right for it to be acknowledged, a hardware
subroutine call to the requested service routine will be the next
instruction to be executed. The call itself takes two cycles. Thus, a
minimum of three complete machine cycles elapse between
activation of an external interrupt request and the beginning of
execution of the first instruction of the service routine. Figure 25
shows interrupt response timings.
A longer response time would result if the request is blocked by one
of the 3 previously listed conditions. If an interrupt of equal or higher
priority level is already in progress, the additional wait time obviously
depends on the nature of the other interrupt’s service routine. If the
instruction in progress is not in its final cycle, the additional wait time
cannot be more the 3 cycles, since the longest instructions (MUL
and DIV) are only 4 cycles long, and if the instruction in progress is
RETI or an access to IE or IP, the additional wait time cannot be
more than 5 cycles (a maximum of one more cycle to complete the
instruction in progress, plus 4 cycles to complete the next instruction
if the instruction is MUL or DIV).
Thus, in a single-interrupt system, the response time is always more
than 3 cycles and less than 9 cycles.
As previously mentioned, the derivatives described in this data
sheet have a four-level interrupt structure. The corresponding
registers are IE, IP and IPH. (See Figures 22, 23, and 24.) The IPH
(Interrupt Priority High) register makes the four-level interrupt
structure possible.
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPH.x
IP.x
INTERRUPT PRIORITY LEVEL
0
Level 0 (lowest priority)
0
1
Level 1
1
0
Level 2
1
Level 3 (highest priority)
相關PDF資料 |
PDF描述 |
|---|---|
| USB-B-S-F-B-TH-R | USB TYPE B 2.0 BLACK T/H |
| USB-B-S-F-B-TH | CONN USB 4POS 2.5MM RA T/H TERM |
| 87520-1110BLF | 1110BLF USB S/D RECEPT |
| 87520-1110ALF | 1110ALF USB S/D RECEPT LF |
| 87520-0210BLF | 0210BLF USB S/D RECEPT LF |
相關代理商/技術參數 |
參數描述 |
|---|---|
| P87C52X2FA | 功能描述:8位微控制器 -MCU 80C51 8K/256 OTP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P87C52X2FA,512 | 功能描述:8位微控制器 -MCU 80C51 8K/256 OTP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P87C52X2FA512 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 33MHZ PLCC-44 制造商:NXP 功能描述: |
| P87C52X2FBD | 功能描述:8位微控制器 -MCU 8K/256 OTP 12/6 CLK COMM LQFP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P87C52X2FBD,157 | 功能描述:8位微控制器 -MCU 8K/256 OTP 12/6 CLK RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復。