參數(shù)資料
型號: P87C52X2BN,112
廠商: NXP Semiconductors
文件頁數(shù): 35/62頁
文件大小: 0K
描述: IC 80C51 MCU 8K OTP 40-DIP
產(chǎn)品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 9
系列: 87C
核心處理器: 8051
芯體尺寸: 8-位
速度: 33MHz
連通性: EBI/EMI,UART/USART
外圍設(shè)備: POR
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: OTP
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
產(chǎn)品目錄頁面: 705 (CN2011-ZH PDF)
其它名稱: 568-1013-5
935269601112
P87C52X2BN
Philips Semiconductors
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
2003 Jan 24
40
AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE, 5 V
±10% OPERATION)
Tamb = 0 °C to +70 °C or –40 °C to +85 °C ; VCC = 5 V ±10%, VSS = 0 V1,2,3,4
Symbol
Figure
Parameter
Limits
16 MHz Clock
Unit
MIN
MAX
MIN
MAX
1/tCLCL
31
Oscillator frequency
0
33
MHz
tLHLL
27
ALE pulse width
2 tCLCL–8
117
ns
tAVLL
27
Address valid to ALE low
tCLCL –13
49.5
ns
tLLAX
27
Address hold after ALE low
tCLCL –20
42.5
ns
tLLIV
27
ALE low to valid instruction in
4 tCLCL –35
215
ns
tLLPL
27
ALE low to PSEN low
tCLCL –10
52.5
ns
tPLPH
27
PSEN pulse width
3 tCLCL –10
177.5
ns
tPLIV
27
PSEN low to valid instruction in
3 tCLCL –35
152.5
ns
tPXIX
27
Input instruction hold after PSEN
0
0
ns
tPXIZ
27
Input instruction float after PSEN
tCLCL –10
52.5
ns
tAVIV
27
Address to valid instruction in
5 tCLCL –35
277.5
ns
tPLAZ
27
PSEN low to address float
10
10
ns
Data Memory
tRLRH
28
RD pulse width
6 tCLCL –20
355
ns
tWLWH
29
WR pulse width
6 tCLCL –20
355
ns
tRLDV
28
RD low to valid data in
5 tCLCL –35
277.5
ns
tRHDX
28
Data hold after RD
0
0
ns
tRHDZ
28
Data float after RD
2 tCLCL –10
115
ns
tLLDV
28
ALE low to valid data in
8 tCLCL –35
465
ns
tAVDV
28
Address to valid data in
9 tCLCL –35
527.5
ns
tLLWL
28, 29
ALE low to RD or WR low
3 tCLCL –15
3 tCLCL +15
172.5
202.5
ns
tAVWL
28, 29
Address valid to WR low or RD low
4 tCLCL –15
235
ns
tQVWX
29
Data valid to WR transition
tCLCL –25
37.5
ns
tWHQX
29
Data hold after WR
tCLCL –15
47.5
ns
tQVWH
29
Data valid to WR high
7 tCLCL –5
432.5
ns
tRLAZ
28
RD low to address float
0
0
ns
tWHLH
28, 29
RD or WR high to ALE high
tCLCL –10
tCLCL +10
52.5
72.5
ns
External Clock
tCHCX
31
High time
0.32 tCLCL
tCLCL – tCLCX
ns
tCLCX
31
Low time
0.32 tCLCL
tCLCL – tCHCX
ns
tCLCH
31
Rise time
5
ns
tCHCL
31
Fall time
5
ns
Shift register
tXLXL
30
Serial port clock cycle time
12 tCLCL
750
ns
tQVXH
30
Output data setup to clock rising edge
10 tCLCL –25
600
ns
tXHQX
30
Output data hold after clock rising edge
2 tCLCL –15
110
ns
tXHDX
30
Input data hold after clock rising edge
0
0
ns
tXHDV
30
Clock rising edge to input data valid
10 tCLCL –133
492
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all outputs = 80 pF
3. Interfacing the microcontroller to devices with float time up to 45 ns is permitted. This limited bus contention will not cause damage to port 0
drivers.
4. Parts are guaranteed by design to operate down to 0 Hz.
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