參數(shù)資料
型號(hào)： P87C557E8
廠商： NXP Semiconductors N.V.
元件分類： 8位微控制器
英文描述： 8 BIT MICROCONTROLLER
中文描述： 8位微控制器
文件頁(yè)數(shù)： 41/84頁(yè)
文件大?。?/td> 322K
代理商： P87C557E8
1999 Mar 12
41
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
14.2
Interrupt Handling
The interrupt sources are sampled at S5P2 of every
machine cycle. The samples are polled during the
following machine cycle. If one of the flags was in a set
condition at S5P2 of the previous machine cycle, the
polling cycle will detect it and the interrupt system will
generate an LCALL to the appropriate service routine,
provided this hardware generated LCALL is not blocked by
any of the following conditions:
1.
An interrupt of higher or equal priority level is already
in progress.
2.
The current machine cycle is not the final cycle in the
execution of the instruction in progress. (No interrupt
request will be serviced until the instruction in progress
is completed.).
3.
The instruction in progress is RETI or any access to
the interrupt priority or interrupt enable registers.
(No interrupt will be serviced after RETI or after a read
or write to IP0, IP1, IE0, or IE1 until at least one other
instruction has been subsequently executed.).
The polling cycle is repeated every machine cycle, and the
values polled are the values present at S5P2 of the
previous machine cycle. Note that if an interrupt flag is
active but is not being responded to because of one of the
above conditions, and if the flag is inactive when the
blocking condition is removed, then the blocked interrupt
will not be serviced. Thus, the fact that the interrupt flag
was once active but not serviced is not remembered.
Every polling cycle is new.
The processor acknowledges an interrupt request by
executing a hardware-generated LCALL to the appropriate
service routine. In some cases it also clears the flag which
generated the interrupt, and in others it does not. It clears
the Timer 0, Timer 1, and external interrupt flags.
An external interrupt flag (IE0 or IE1) is cleared only if it
was transition-activated. All other interrupt flags are not
cleared by hardware and must be cleared by the software.
The LCALL pushes the contents of the program counter on
to the stack (but it does not save the PSW) and reloads the
PC with an address that depends on the source of the
interrupt being vectored to as shown in Table 60.
Execution proceeds from the vector address until the RETI
instruction is encountered. The RETI instruction clears the
‘priority level active’ flip-flop that was set when this
interrupt was acknowledged. It then pops the top two bytes
from the stack and reloads the program counter. Execution
of the interrupted program continues from where it was
interrupted.
14.3
Interrupt Priority Structure
Each interrupt source can be assigned one of two priority
levels: high and low. Interrupt priority levels are defined by
the interrupt priority SFRs IP0 and IP1, which are
described in Tables 66 and 68.
Interrupt priority levels are as follows:
logic 0 = low priority
logic 1 = high priority.
A low priority interrupt may be interrupted by a high priority
interrupt. A high priority interrupt cannot be interrupted by
any other interrupt source. If two requests of different
priority occur simultaneously, the high priority level request
is serviced. If requests of the same priority are received
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority level,
there is a second priority structure determined by the
polling sequence. This second priority structure is shown
in Table 60.
14.4
Interrupt vectors
The vector indicates the Program Memory location where
the appropriate interrupt service routine starts; Table 60.
Table 60
Interrupt vectors and priority structure
Note
1.
X0 has the highest priority; T2 the lowest.
SOURCE
SYMBOL
(1)
VECTOR
ADDRESS
(HEX)
External 0
Serial I/O: SIO1 (I
2
C-bus)
ADC completion
Timer 0 overflow
T2 capture 0
T2 compare 0
External 1/ seconds interrupt X1/SEC
T2 capture 1
T2 compare 1
Timer 1 overflow
T2 capture 2
T2 compare 2
Serial I/O SIO0 (UART)
T2 capture 3
T2 overflow
X0 (highest)
S1
ADC
T0
CT0
CM0
0003
002B
0053
000B
0033
005B
0013
0033
0063
001B
0043
006B
0023
004B
0073
CT1
CM1
T1
CT2
CM2
S0
CT3
T2 (lowest)
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