參數(shù)資料
型號(hào)： P87C557E8
廠商： NXP Semiconductors N.V.
元件分類： 8位微控制器
英文描述： 8 BIT MICROCONTROLLER
中文描述： 8位微控制器
文件頁(yè)數(shù)： 48/84頁(yè)
文件大小： 322K
代理商： P87C557E8
1999 Mar 12
48
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
16 OSCILLATOR CIRCUITS
16.1
XTAL1; XTAL2 oscillator: standard 80C51
The XTAL1; XTAL2 oscillator: standard 80C51 is selected
when input SELXTAL1 = 1. The oscillator circuit is a
single-stage inverting amplifier in a Pierce oscillator
configuration. The circuitry between pins XTAL1 and
XTAL2 is basically an inverter biased to the transfer point.
Either a crystal or ceramic resonator can be used as the
feedback element to complete the oscillator circuitry. Both
are operated in parallel resonance.
XTAL1 is the high gain amplifier input, and XTAL2 is the
output; see Fig.17. To drive the P8xC557E8 externally,
XTAL1 is driven from an external source and XTAL2 is left
open-circuit; see Fig.18.
When the ‘XTAL1; XTAL2 oscillator’ is selected the
‘XTAL3; XTAL4 oscillator’ is halted; pins XTAL3 and
XTAL4 must not be connected.
16.2
XTAL3; XTAL4 oscillator: 32 kHz PLL oscillator
(with Seconds timer)
The XTAL3; XTAL4 oscillator: 32 kHz oscillator and the
Phase Locked Loop (PLL) are selected when
SELXTAL1 = 0 (XTAL1; XTAL2 oscillator is halted). In this
case pin XTAL2 is kept floating.
16.2.1
32
K
H
Z OSCILLATOR
The 32 kHz oscillator consists of an inverter, which forms
a Pierce oscillator with the on-chip components C1, C2, R
f
and an external crystal of 32768 Hz. The inverter is
switched to 3-state and pin XTAL3 is pulled to V
SS
:
During Power-down mode, when RUN32
(PLLCON.7) = 0
During reset, RSTIN = 1
When the XTAL1; XTAL2 oscillator is selected
(SELXTAL1 = 1).
16.2.2
PLL C
URRENT
C
ONTROLLED
O
SCILLATOR
A Current Controlled Oscillator (CCO) generates a clock
frequency f
CCO
of approximately 32, 38, 44 or 50 MHz.
This CCO is controlled by the PLL, with the 32 kHz
oscillator as the reference clock.
The system clock frequency f
clk
is derived from f
CCO
and
can be varied under software control by changing the
contents of the PLL Control Register (PLLCON) bits
FSEL.4 to FSEL.0. The CCO frequency f
CCO
can be
changed via the PLLCON bits FSEL.1 and FSEL.0 and the
maximum locking time is 10 ms (this parameter is
characterized). During the stabilization phase, no time
critical routines should be executed.
Changing f
clk
has to be done in two steps:
From
high
to
low
frequencies; first change
FSEL.4 to FSEL.2, then FSEL.1 to FSEL.0
From
low
to
high
frequencies; first change
FSEL.1 to FSEL.0 only, and after a stabilization phase
of 10 ms, change FSEL.4 to FSEL.2.
If only FSEL.4 to FSEL.2 is changed, and FSEL.1 to
FSEL.0 not, then it takes approximately 1
μ
s until the new
frequency is available. The frequency selection is shown in
Table 73.
16.2.3
PLL C
ONTROL
R
EGISTER
(PLLCON)
PLLCON is a Special Function Register, which can be
read and written by software. It contains the control bits:
to select the system clock frequencies (f
clk
)
the seconds interrupt flag (SECINT)
to enable the seconds interrupt flag (ENSECI)
the RUN32 bit, which defines if during Power-down
mode the 32 kHz oscillator is halted or not.
PLLCON is initialized to 0DH upon reset (RSTIN = 1) or
Watchdog Timer overflow. PLLCON = 0DH corresponds
to a system clock frequency f
clk
= 11.01 MHz.
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